Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	127	1			T3	1		T25	1		T28	1
auto_req_mode	147	1			T9	1		T10	1		T11	1
sw_mode	2928	1			T1	15		T2	1		T24	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

304

1

T9

1

T10

1

T24

1

single

96

1

T2

1

T3

1

T11

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1340	1			T2	1		T9	1		T10	1
auto[2]	157	1			T3	1		T28	1		T129	1
auto[3]	40	1			T131	1		T13	1		T148	1
auto[4]	146	1			T4	14		T130	1		T277	1
auto[5]	130	1			T126	61		T278	1		T279	1
auto[6]	61	1			T128	1		T134	1		T280	1
auto[7]	1328	1			T1	15		T25	1		T5	3

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	80	1			T106	1		T26	1		T90	1
auto[1]	auto_req_mode	86	1			T9	1		T10	1		T11	1
auto[1]	sw_mode	1174	1			T2	1		T24	1		T111	1
auto[2]	boot_req_mode	5	1			T3	1		T28	1		T281	1
auto[2]	auto_req_mode	1	1			T12	1		-	-		-	-
auto[2]	sw_mode	151	1			T129	1		T282	1		T283	1
auto[3]	boot_req_mode	2	1			T284	1		T285	1		-	-
auto[3]	auto_req_mode	7	1			T131	1		T13	1		T148	1
auto[3]	sw_mode	31	1			T144	1		T286	1		T287	5
auto[4]	boot_req_mode	5	1			T277	1		T288	1		T289	1
auto[4]	auto_req_mode	7	1			T130	1		T14	1		T290	1
auto[4]	sw_mode	134	1			T4	14		T291	1		T292	1
auto[5]	boot_req_mode	3	1			T242	1		T293	1		T294	1
auto[5]	auto_req_mode	4	1			T278	1		T279	1		T295	1
auto[5]	sw_mode	123	1			T126	61		T215	11		T296	12
auto[6]	boot_req_mode	2	1			T297	1		T298	1		-	-
auto[6]	auto_req_mode	1	1			T299	1		-	-		-	-
auto[6]	sw_mode	58	1			T128	1		T134	1		T280	1
auto[7]	boot_req_mode	30	1			T25	1		T110	1		T127	1
auto[7]	auto_req_mode	41	1			T49	1		T149	1		T150	1
auto[7]	sw_mode	1257	1			T1	15		T5	3		T109	1