Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	603027	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4771432

1

T1

28429

T2

22

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1429894	1			T1	8049		T2	46		T3	42
values[0x0]	1823937	1			T1	10811		T2	8		T3	14
values[0x1]	2120628	1			T1	12622		T2	14		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	301447	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5073012

1

T1

30086

T2

33

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21848	1			T1	120		T2	2		T128	5
valid_sources[0x01]	22469	1			T1	128		T4	2		T111	1
valid_sources[0x02]	19959	1			T1	118		T4	4		T111	1
valid_sources[0x03]	19865	1			T1	118		T3	1		T4	2
valid_sources[0x04]	22013	1			T1	147		T3	2		T4	2
valid_sources[0x05]	20719	1			T1	103		T22	2		T127	1
valid_sources[0x06]	21082	1			T1	114		T4	2		T127	3
valid_sources[0x07]	18699	1			T1	130		T4	2		T127	2
valid_sources[0x08]	20946	1			T1	168		T25	3		T4	3
valid_sources[0x09]	21084	1			T1	125		T4	3		T22	1
valid_sources[0x0a]	22019	1			T1	150		T3	1		T4	2
valid_sources[0x0b]	20663	1			T1	146		T3	1		T4	2
valid_sources[0x0c]	21562	1			T1	118		T4	8		T111	2
valid_sources[0x0d]	22643	1			T1	133		T4	7		T5	1
valid_sources[0x0e]	20991	1			T1	102		T21	1		T127	2
valid_sources[0x0f]	21972	1			T1	119		T5	4		T127	1
valid_sources[0x10]	22543	1			T1	144		T4	6		T127	3
valid_sources[0x11]	21533	1			T1	127		T4	3		T22	3
valid_sources[0x12]	21860	1			T1	114		T3	1		T9	3
valid_sources[0x13]	19379	1			T1	130		T9	1		T25	6
valid_sources[0x14]	19671	1			T1	132		T4	2		T128	1
valid_sources[0x15]	22519	1			T1	115		T4	1		T127	2
valid_sources[0x16]	21636	1			T1	121		T25	1		T4	1
valid_sources[0x17]	20420	1			T1	128		T2	1		T9	1
valid_sources[0x18]	21484	1			T1	112		T9	4		T5	4
valid_sources[0x19]	19999	1			T1	107		T2	2		T4	4
valid_sources[0x1a]	22461	1			T1	103		T4	3		T16	1
valid_sources[0x1b]	20116	1			T1	117		T4	1		T28	6
valid_sources[0x1c]	20583	1			T1	128		T2	3		T4	1
valid_sources[0x1d]	19855	1			T1	122		T4	7		T128	1
valid_sources[0x1e]	20142	1			T1	123		T25	4		T5	2
valid_sources[0x1f]	21653	1			T1	131		T2	2		T3	1
valid_sources[0x20]	20736	1			T1	136		T5	1		T127	4
valid_sources[0x21]	19193	1			T1	122		T4	4		T128	2
valid_sources[0x22]	21761	1			T1	104		T3	2		T25	13
valid_sources[0x23]	21172	1			T1	137		T25	3		T4	3
valid_sources[0x24]	19412	1			T1	136		T4	9		T127	4
valid_sources[0x25]	21868	1			T1	125		T4	3		T111	2
valid_sources[0x26]	19888	1			T1	120		T3	1		T25	2
valid_sources[0x27]	21691	1			T1	109		T3	1		T4	2
valid_sources[0x28]	23275	1			T1	131		T4	11		T16	1
valid_sources[0x29]	22255	1			T1	119		T2	2		T4	8
valid_sources[0x2a]	19482	1			T1	109		T3	1		T4	5
valid_sources[0x2b]	21219	1			T1	116		T4	7		T112	2
valid_sources[0x2c]	22620	1			T1	131		T2	5		T4	1
valid_sources[0x2d]	20983	1			T1	104		T9	9		T4	4
valid_sources[0x2e]	21298	1			T1	119		T4	7		T5	1
valid_sources[0x2f]	20884	1			T1	144		T3	1		T25	12
valid_sources[0x30]	20134	1			T1	126		T4	6		T112	1
valid_sources[0x31]	20884	1			T1	119		T112	1		T21	2
valid_sources[0x32]	23088	1			T1	123		T2	1		T9	2
valid_sources[0x33]	20373	1			T1	141		T4	1		T5	10
valid_sources[0x34]	20000	1			T1	136		T4	5		T112	1
valid_sources[0x35]	20517	1			T1	124		T11	116		T4	2
valid_sources[0x36]	19562	1			T1	119		T3	3		T4	3
valid_sources[0x37]	21362	1			T1	132		T4	2		T23	2
valid_sources[0x38]	21414	1			T1	114		T2	1		T3	1
valid_sources[0x39]	20831	1			T1	101		T4	3		T23	1
valid_sources[0x3a]	21357	1			T1	116		T9	2		T4	2
valid_sources[0x3b]	22477	1			T1	137		T2	2		T4	6
valid_sources[0x3c]	22846	1			T1	129		T3	1		T25	5
valid_sources[0x3d]	20985	1			T1	123		T4	4		T112	1
valid_sources[0x3e]	20650	1			T1	142		T2	1		T4	6
valid_sources[0x3f]	22809	1			T1	153		T3	1		T4	5
valid_sources[0x40]	20140	1			T1	110		T2	1		T4	16
valid_sources[0x41]	20217	1			T1	128		T4	4		T128	3
valid_sources[0x42]	21910	1			T1	114		T4	1		T127	1
valid_sources[0x43]	21264	1			T1	109		T3	1		T4	2
valid_sources[0x44]	19682	1			T1	127		T2	2		T9	13
valid_sources[0x45]	20169	1			T1	125		T3	1		T4	11
valid_sources[0x46]	18720	1			T1	110		T4	3		T5	12
valid_sources[0x47]	19358	1			T1	138		T9	2		T4	3
valid_sources[0x48]	20431	1			T1	101		T25	5		T4	7
valid_sources[0x49]	20082	1			T1	115		T4	4		T111	1
valid_sources[0x4a]	21151	1			T1	104		T2	1		T4	1
valid_sources[0x4b]	19412	1			T1	126		T9	2		T4	4
valid_sources[0x4c]	21166	1			T1	133		T4	3		T5	2
valid_sources[0x4d]	21904	1			T1	117		T4	4		T111	2
valid_sources[0x4e]	20265	1			T1	128		T2	2		T5	1
valid_sources[0x4f]	21988	1			T1	115		T3	1		T25	3
valid_sources[0x50]	20786	1			T1	129		T9	5		T4	5
valid_sources[0x51]	20524	1			T1	131		T9	3		T4	1
valid_sources[0x52]	21152	1			T1	112		T9	3		T4	4
valid_sources[0x53]	21347	1			T1	125		T3	1		T9	2
valid_sources[0x54]	21427	1			T1	114		T10	134		T4	3
valid_sources[0x55]	20262	1			T1	132		T4	4		T28	1
valid_sources[0x56]	22166	1			T1	129		T4	7		T29	18
valid_sources[0x57]	19639	1			T1	126		T4	2		T127	1
valid_sources[0x58]	19575	1			T1	95		T9	2		T25	13
valid_sources[0x59]	21088	1			T1	124		T4	6		T23	1
valid_sources[0x5a]	20676	1			T1	107		T25	2		T4	2
valid_sources[0x5b]	21317	1			T1	122		T25	20		T4	3
valid_sources[0x5c]	19120	1			T1	144		T4	2		T128	1
valid_sources[0x5d]	20130	1			T1	116		T2	1		T4	5
valid_sources[0x5e]	24031	1			T1	154		T4	5		T29	19
valid_sources[0x5f]	19002	1			T1	116		T4	4		T106	4
valid_sources[0x60]	20294	1			T1	133		T2	1		T4	6
valid_sources[0x61]	20797	1			T1	143		T25	2		T4	2
valid_sources[0x62]	21072	1			T1	122		T2	3		T4	2
valid_sources[0x63]	20096	1			T1	118		T9	4		T4	2
valid_sources[0x64]	21015	1			T1	134		T25	14		T4	3
valid_sources[0x65]	20440	1			T1	132		T4	4		T128	1
valid_sources[0x66]	20843	1			T1	109		T3	1		T4	2
valid_sources[0x67]	21144	1			T1	152		T25	8		T4	3
valid_sources[0x68]	20295	1			T1	117		T16	1		T112	1
valid_sources[0x69]	21143	1			T1	180		T4	1		T111	1
valid_sources[0x6a]	19981	1			T1	106		T3	1		T4	9
valid_sources[0x6b]	20161	1			T1	113		T4	11		T23	1
valid_sources[0x6c]	20518	1			T1	126		T3	1		T4	3
valid_sources[0x6d]	21830	1			T1	106		T4	1		T128	2
valid_sources[0x6e]	20672	1			T1	130		T25	4		T4	1
valid_sources[0x6f]	21396	1			T1	106		T3	1		T25	1
valid_sources[0x70]	19714	1			T1	123		T3	1		T4	2
valid_sources[0x71]	19815	1			T1	138		T2	2		T4	2
valid_sources[0x72]	20098	1			T1	121		T3	1		T4	2
valid_sources[0x73]	20360	1			T1	130		T25	3		T4	2
valid_sources[0x74]	20311	1			T1	120		T25	1		T4	2
valid_sources[0x75]	20503	1			T1	120		T4	1		T12	2
valid_sources[0x76]	20854	1			T1	128		T3	1		T4	3
valid_sources[0x77]	20571	1			T1	116		T2	2		T9	5
valid_sources[0x78]	22497	1			T1	108		T4	3		T28	3
valid_sources[0x79]	20860	1			T1	119		T3	2		T9	8
valid_sources[0x7a]	20227	1			T1	124		T2	2		T4	2
valid_sources[0x7b]	20083	1			T1	97		T4	1		T5	14
valid_sources[0x7c]	23395	1			T1	115		T3	2		T4	2
valid_sources[0x7d]	19947	1			T1	120		T9	1		T4	3
valid_sources[0x7e]	21559	1			T1	129		T2	4		T25	2
valid_sources[0x7f]	19395	1			T1	113		T25	4		T127	2
valid_sources[0x80]	21486	1			T1	94		T9	2		T25	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1203657

1

T1

7192

T2

3

T3

4

values[0x0]

all_enables

biggest_size

1784898

1

T1

10603

T2

7

T3

14

values[0x1]

all_enables

biggest_size

1782877

1

T1

10634

T2

12

T3

9