Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2752	1			T1	12		T2	2		T3	1
non_zero_bins[1]	1917	1			T1	8		T3	1		T9	1
zero	8692	1			T1	35		T2	2		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	563	1			T1	4		T2	1		T3	1
uni	3707	1			T1	17		T2	1		T3	2
gen	4117	1			T1	15		T2	1		T3	2
res	820	1			T1	2		T9	1		T10	3
ins	4154	1			T1	17		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9057

1

T1

42

T2

2

T3

4

mubi_true

4304

1

T1

13

T2

2

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

13361

1

T1

55

T2

4

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	126	1			T1	2		T28	1		T127	1
upd	non_zero_bins[0]	pass	mubi_true	131	1			T1	1		T3	1		T4	1
upd	non_zero_bins[1]	pass	mubi_false	94	1			T1	1		T125	1		T126	2
upd	non_zero_bins[1]	pass	mubi_true	89	1			T125	2		T250	1		T126	2
upd	zero	pass	mubi_false	62	1			T2	1		T4	1		T5	1
upd	zero	pass	mubi_true	61	1			T125	2		T251	1		T135	1
uni	zero	pass	mubi_false	2745	1			T1	16		T2	1		T3	2
uni	zero	pass	mubi_true	962	1			T1	1		T4	5		T109	1
gen	non_zero_bins[0]	pass	mubi_false	536	1			T11	3		T25	1		T109	1
gen	non_zero_bins[0]	pass	mubi_true	529	1			T1	3		T2	1		T4	3
gen	non_zero_bins[1]	pass	mubi_false	341	1			T1	2		T49	3		T125	2
gen	non_zero_bins[1]	pass	mubi_true	403	1			T1	1		T10	4		T4	2
gen	zero	pass	mubi_false	1896	1			T1	8		T3	1		T11	1
gen	zero	pass	mubi_true	412	1			T1	1		T3	1		T25	1
res	non_zero_bins[0]	pass	mubi_false	192	1			T24	1		T4	1		T22	1
res	non_zero_bins[0]	pass	mubi_true	187	1			T1	1		T9	1		T11	2
res	non_zero_bins[1]	pass	mubi_false	132	1			T1	1		T10	1		T25	1
res	non_zero_bins[1]	pass	mubi_true	130	1			T21	3		T12	2		T125	1
res	zero	pass	mubi_false	109	1			T52	5		T60	2		T34	1
res	zero	pass	mubi_true	70	1			T10	2		T110	1		T125	2
ins	non_zero_bins[0]	pass	mubi_false	543	1			T1	2		T9	1		T24	1
ins	non_zero_bins[0]	pass	mubi_true	508	1			T1	3		T2	1		T4	1
ins	non_zero_bins[1]	pass	mubi_false	357	1			T1	1		T3	1		T10	2
ins	non_zero_bins[1]	pass	mubi_true	371	1			T1	2		T9	1		T11	1
ins	zero	pass	mubi_false	1924	1			T1	9		T25	1		T4	8
ins	zero	pass	mubi_true	451	1			T3	1		T23	1		T5	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded