Module Definition
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Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Module : edn_ack_sm
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T10,T23

FSM Coverage for Module : edn_ack_sm
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T1,T2,T3
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T15,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T97,T172,T173
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T2,T3
DataWait->AckPls 80 Covered T1,T2,T3
DataWait->Disabled 107 Covered T10,T23,T174
DataWait->Error 99 Covered T15,T82,T140
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T21,T90,T175
EndPointClear->Error 99 Covered T7,T27,T88
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T1,T9,T10
Idle->Error 99 Covered T15,T6,T16



Branch Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T2,T3
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T2,T3
DataWait - - - 0 Covered T1,T2,T3
AckPls - - - - Covered T1,T2,T3
Error - - - - Covered T15,T6,T16
default - - - - Covered T6,T7,T8


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T15,T6,T16
0 1 Covered T9,T10,T23
0 0 Covered T1,T2,T3


Assert Coverage for Module : edn_ack_sm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 1367686411 907835 0 0
FpvSecCmErrorStEscalate_A 1367686411 914226 0 0
u_state_regs_A 1367646764 1366524741 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1367686411 907835 0 0
T6 11802 4528 0 0
T7 0 2715 0 0
T8 0 7713 0 0
T15 4886 2464 0 0
T16 14854 7686 0 0
T17 0 7616 0 0
T21 11515 0 0 0
T27 0 1204 0 0
T41 0 4473 0 0
T105 0 7931 0 0
T106 7882 0 0 0
T107 0 2870 0 0
T109 17311 0 0 0
T110 12915 0 0 0
T111 9975 0 0 0
T112 7868 0 0 0
T113 6244 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1367686411 914226 0 0
T6 11802 4535 0 0
T7 0 2722 0 0
T8 0 7720 0 0
T15 4886 2471 0 0
T16 14854 7693 0 0
T17 0 7623 0 0
T21 11515 0 0 0
T27 0 1211 0 0
T41 0 4480 0 0
T105 0 7938 0 0
T106 7882 0 0 0
T107 0 2877 0 0
T109 17311 0 0 0
T110 12915 0 0 0
T111 9975 0 0 0
T112 7868 0 0 0
T113 6244 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1367646764 1366524741 0 0
T1 898961 898905 0 0
T2 9975 9492 0 0
T3 15316 14938 0 0
T4 168070 163870 0 0
T9 15715 15190 0 0
T10 22890 22470 0 0
T11 38206 37646 0 0
T23 22407 21959 0 0
T24 19663 19257 0 0
T25 31668 31052 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T10,T23

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T10,T109,T127
DataWait 75 Covered T10,T109,T127
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T15,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T10,T109,T127
DataWait->AckPls 80 Covered T10,T109,T127
DataWait->Disabled 107 Covered T10,T176
DataWait->Error 99 Covered T82,T140,T77
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T21,T90,T175
EndPointClear->Error 99 Covered T7,T27,T88
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T10,T109,T127
Idle->Disabled 107 Covered T1,T9,T10
Idle->Error 99 Covered T15,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T10,T109,T127
Idle - 1 0 - Covered T10,T109,T127
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T10,T109,T127
DataWait - - - 0 Covered T10,T109,T127
AckPls - - - - Covered T10,T109,T127
Error - - - - Covered T15,T6,T16
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T15,T6,T16
0 1 Covered T9,T10,T23
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 195383773 130005 0 0
FpvSecCmErrorStEscalate_A 195383773 130918 0 0
u_state_regs_A 195383773 195223484 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130005 0 0
T6 1686 654 0 0
T7 0 395 0 0
T8 0 1109 0 0
T15 698 352 0 0
T16 2122 1098 0 0
T17 0 1088 0 0
T21 1645 0 0 0
T27 0 172 0 0
T41 0 639 0 0
T105 0 1133 0 0
T106 1126 0 0 0
T107 0 410 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130918 0 0
T6 1686 655 0 0
T7 0 396 0 0
T8 0 1110 0 0
T15 698 353 0 0
T16 2122 1099 0 0
T17 0 1089 0 0
T21 1645 0 0 0
T27 0 173 0 0
T41 0 640 0 0
T105 0 1134 0 0
T106 1126 0 0 0
T107 0 411 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 195223484 0 0
T1 128423 128415 0 0
T2 1425 1356 0 0
T3 2188 2134 0 0
T4 24010 23410 0 0
T9 2245 2170 0 0
T10 3270 3210 0 0
T11 5458 5378 0 0
T23 3201 3137 0 0
T24 2809 2751 0 0
T25 4524 4436 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T10,T23

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T23,T127,T49
DataWait 75 Covered T23,T127,T49
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T15,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T23,T127,T49
DataWait->AckPls 80 Covered T23,T127,T49
DataWait->Disabled 107 Covered T23,T40,T177
DataWait->Error 99 Covered T79,T38,T178
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T21,T90,T175
EndPointClear->Error 99 Covered T7,T27,T88
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T23,T127,T49
Idle->Disabled 107 Covered T1,T9,T10
Idle->Error 99 Covered T15,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T23,T127,T49
Idle - 1 0 - Covered T23,T127,T49
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T23,T127,T49
DataWait - - - 0 Covered T23,T127,T49
AckPls - - - - Covered T23,T127,T49
Error - - - - Covered T15,T6,T16
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T15,T6,T16
0 1 Covered T9,T10,T23
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 195383773 130005 0 0
FpvSecCmErrorStEscalate_A 195383773 130918 0 0
u_state_regs_A 195383773 195223484 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130005 0 0
T6 1686 654 0 0
T7 0 395 0 0
T8 0 1109 0 0
T15 698 352 0 0
T16 2122 1098 0 0
T17 0 1088 0 0
T21 1645 0 0 0
T27 0 172 0 0
T41 0 639 0 0
T105 0 1133 0 0
T106 1126 0 0 0
T107 0 410 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130918 0 0
T6 1686 655 0 0
T7 0 396 0 0
T8 0 1110 0 0
T15 698 353 0 0
T16 2122 1099 0 0
T17 0 1089 0 0
T21 1645 0 0 0
T27 0 173 0 0
T41 0 640 0 0
T105 0 1134 0 0
T106 1126 0 0 0
T107 0 411 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 195223484 0 0
T1 128423 128415 0 0
T2 1425 1356 0 0
T3 2188 2134 0 0
T4 24010 23410 0 0
T9 2245 2170 0 0
T10 3270 3210 0 0
T11 5458 5378 0 0
T23 3201 3137 0 0
T24 2809 2751 0 0
T25 4524 4436 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T10,T23

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T23,T29,T127
DataWait 75 Covered T23,T29,T127
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T15,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T23,T29,T127
DataWait->AckPls 80 Covered T23,T29,T127
DataWait->Disabled 107 Covered T179,T180
DataWait->Error 99 Covered T56,T104,T181
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T21,T90,T175
EndPointClear->Error 99 Covered T7,T27,T88
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T23,T29,T127
Idle->Disabled 107 Covered T1,T9,T10
Idle->Error 99 Covered T15,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T23,T29,T127
Idle - 1 0 - Covered T23,T29,T127
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T23,T29,T127
DataWait - - - 0 Covered T23,T29,T127
AckPls - - - - Covered T23,T29,T127
Error - - - - Covered T15,T6,T16
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T15,T6,T16
0 1 Covered T9,T10,T23
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 195383773 130005 0 0
FpvSecCmErrorStEscalate_A 195383773 130918 0 0
u_state_regs_A 195383773 195223484 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130005 0 0
T6 1686 654 0 0
T7 0 395 0 0
T8 0 1109 0 0
T15 698 352 0 0
T16 2122 1098 0 0
T17 0 1088 0 0
T21 1645 0 0 0
T27 0 172 0 0
T41 0 639 0 0
T105 0 1133 0 0
T106 1126 0 0 0
T107 0 410 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130918 0 0
T6 1686 655 0 0
T7 0 396 0 0
T8 0 1110 0 0
T15 698 353 0 0
T16 2122 1099 0 0
T17 0 1089 0 0
T21 1645 0 0 0
T27 0 173 0 0
T41 0 640 0 0
T105 0 1134 0 0
T106 1126 0 0 0
T107 0 411 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 195223484 0 0
T1 128423 128415 0 0
T2 1425 1356 0 0
T3 2188 2134 0 0
T4 24010 23410 0 0
T9 2245 2170 0 0
T10 3270 3210 0 0
T11 5458 5378 0 0
T23 3201 3137 0 0
T24 2809 2751 0 0
T25 4524 4436 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T10,T23

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T109,T21,T22
DataWait 75 Covered T109,T21,T22
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T15,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T109,T21,T22
DataWait->AckPls 80 Covered T109,T21,T22
DataWait->Disabled 107 Covered T22,T182,T183
DataWait->Error 99 Covered T103,T67,T184
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T21,T90,T175
EndPointClear->Error 99 Covered T7,T27,T88
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T109,T21,T22
Idle->Disabled 107 Covered T1,T9,T10
Idle->Error 99 Covered T15,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T109,T21,T22
Idle - 1 0 - Covered T109,T21,T22
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T109,T21,T22
DataWait - - - 0 Covered T109,T21,T22
AckPls - - - - Covered T109,T21,T22
Error - - - - Covered T15,T6,T16
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T15,T6,T16
0 1 Covered T9,T10,T23
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 195383773 130005 0 0
FpvSecCmErrorStEscalate_A 195383773 130918 0 0
u_state_regs_A 195383773 195223484 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130005 0 0
T6 1686 654 0 0
T7 0 395 0 0
T8 0 1109 0 0
T15 698 352 0 0
T16 2122 1098 0 0
T17 0 1088 0 0
T21 1645 0 0 0
T27 0 172 0 0
T41 0 639 0 0
T105 0 1133 0 0
T106 1126 0 0 0
T107 0 410 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130918 0 0
T6 1686 655 0 0
T7 0 396 0 0
T8 0 1110 0 0
T15 698 353 0 0
T16 2122 1099 0 0
T17 0 1089 0 0
T21 1645 0 0 0
T27 0 173 0 0
T41 0 640 0 0
T105 0 1134 0 0
T106 1126 0 0 0
T107 0 411 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 195223484 0 0
T1 128423 128415 0 0
T2 1425 1356 0 0
T3 2188 2134 0 0
T4 24010 23410 0 0
T9 2245 2170 0 0
T10 3270 3210 0 0
T11 5458 5378 0 0
T23 3201 3137 0 0
T24 2809 2751 0 0
T25 4524 4436 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T10,T23

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T1,T2,T3
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T15,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T97,T172,T185
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T2,T3
DataWait->AckPls 80 Covered T1,T2,T3
DataWait->Disabled 107 Covered T39,T186,T187
DataWait->Error 99 Covered T15,T188,T189
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T21,T90,T175
EndPointClear->Error 99 Covered T27,T88,T18
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T1,T9,T10
Idle->Error 99 Covered T16,T17,T105



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T2,T3
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T2,T3
DataWait - - - 0 Covered T1,T2,T3
AckPls - - - - Covered T1,T2,T3
Error - - - - Covered T15,T6,T16
default - - - - Covered T6,T7,T8


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T15,T6,T16
0 1 Covered T9,T10,T23
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 195383773 127805 0 0
FpvSecCmErrorStEscalate_A 195383773 128718 0 0
u_state_regs_A 195344126 195183837 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 127805 0 0
T6 1686 604 0 0
T7 0 345 0 0
T8 0 1059 0 0
T15 698 352 0 0
T16 2122 1098 0 0
T17 0 1088 0 0
T21 1645 0 0 0
T27 0 172 0 0
T41 0 639 0 0
T105 0 1133 0 0
T106 1126 0 0 0
T107 0 410 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 128718 0 0
T6 1686 605 0 0
T7 0 346 0 0
T8 0 1060 0 0
T15 698 353 0 0
T16 2122 1099 0 0
T17 0 1089 0 0
T21 1645 0 0 0
T27 0 173 0 0
T41 0 640 0 0
T105 0 1134 0 0
T106 1126 0 0 0
T107 0 411 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195344126 195183837 0 0
T1 128423 128415 0 0
T2 1425 1356 0 0
T3 2188 2134 0 0
T4 24010 23410 0 0
T9 2245 2170 0 0
T10 3270 3210 0 0
T11 5458 5378 0 0
T23 3201 3137 0 0
T24 2809 2751 0 0
T25 4524 4436 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T10,T23

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T9,T25,T106
DataWait 75 Covered T9,T25,T106
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T15,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T173,T190
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T9,T25,T106
DataWait->AckPls 80 Covered T9,T25,T106
DataWait->Disabled 107 Covered T191,T71,T192
DataWait->Error 99 Covered T32,T193,T194
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T21,T90,T175
EndPointClear->Error 99 Covered T7,T27,T88
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T9,T25,T106
Idle->Disabled 107 Covered T1,T9,T10
Idle->Error 99 Covered T15,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T9,T25,T106
Idle - 1 0 - Covered T9,T25,T106
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T9,T25,T106
DataWait - - - 0 Covered T9,T25,T106
AckPls - - - - Covered T9,T25,T106
Error - - - - Covered T15,T6,T16
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T15,T6,T16
0 1 Covered T9,T10,T23
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 195383773 130005 0 0
FpvSecCmErrorStEscalate_A 195383773 130918 0 0
u_state_regs_A 195383773 195223484 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130005 0 0
T6 1686 654 0 0
T7 0 395 0 0
T8 0 1109 0 0
T15 698 352 0 0
T16 2122 1098 0 0
T17 0 1088 0 0
T21 1645 0 0 0
T27 0 172 0 0
T41 0 639 0 0
T105 0 1133 0 0
T106 1126 0 0 0
T107 0 410 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130918 0 0
T6 1686 655 0 0
T7 0 396 0 0
T8 0 1110 0 0
T15 698 353 0 0
T16 2122 1099 0 0
T17 0 1089 0 0
T21 1645 0 0 0
T27 0 173 0 0
T41 0 640 0 0
T105 0 1134 0 0
T106 1126 0 0 0
T107 0 411 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 195223484 0 0
T1 128423 128415 0 0
T2 1425 1356 0 0
T3 2188 2134 0 0
T4 24010 23410 0 0
T9 2245 2170 0 0
T10 3270 3210 0 0
T11 5458 5378 0 0
T23 3201 3137 0 0
T24 2809 2751 0 0
T25 4524 4436 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T10,T23

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T10,T25,T128
DataWait 75 Covered T10,T25,T128
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T15,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T195
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T10,T25,T128
DataWait->AckPls 80 Covered T10,T25,T128
DataWait->Disabled 107 Covered T174,T85,T87
DataWait->Error 99 Covered T102,T93,T196
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T21,T90,T175
EndPointClear->Error 99 Covered T7,T27,T88
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T10,T25,T128
Idle->Disabled 107 Covered T1,T9,T10
Idle->Error 99 Covered T15,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T10,T25,T128
Idle - 1 0 - Covered T10,T25,T128
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T10,T25,T128
DataWait - - - 0 Covered T10,T25,T128
AckPls - - - - Covered T10,T25,T128
Error - - - - Covered T15,T6,T16
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T15,T6,T16
0 1 Covered T9,T10,T23
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 195383773 130005 0 0
FpvSecCmErrorStEscalate_A 195383773 130918 0 0
u_state_regs_A 195383773 195223484 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130005 0 0
T6 1686 654 0 0
T7 0 395 0 0
T8 0 1109 0 0
T15 698 352 0 0
T16 2122 1098 0 0
T17 0 1088 0 0
T21 1645 0 0 0
T27 0 172 0 0
T41 0 639 0 0
T105 0 1133 0 0
T106 1126 0 0 0
T107 0 410 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 130918 0 0
T6 1686 655 0 0
T7 0 396 0 0
T8 0 1110 0 0
T15 698 353 0 0
T16 2122 1099 0 0
T17 0 1089 0 0
T21 1645 0 0 0
T27 0 173 0 0
T41 0 640 0 0
T105 0 1134 0 0
T106 1126 0 0 0
T107 0 411 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 195223484 0 0
T1 128423 128415 0 0
T2 1425 1356 0 0
T3 2188 2134 0 0
T4 24010 23410 0 0
T9 2245 2170 0 0
T10 3270 3210 0 0
T11 5458 5378 0 0
T23 3201 3137 0 0
T24 2809 2751 0 0
T25 4524 4436 0 0