Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T117,T120
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T122,T123,T124
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	390123474	1039122	0	0
DepthKnown_A	390767546	390446968	0	0
RvalidKnown_A	390767546	390446968	0	0
WreadyKnown_A	390767546	390446968	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	390487844	1128980	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390123474	1039122	0	0
T4	48020	0	0	0
T5	16146	0	0	0
T6	0	181	0	0
T9	4490	2766	0	0
T10	6540	5162	0	0
T11	10916	8031	0	0
T12	0	1678	0	0
T21	0	2464	0	0
T22	0	7174	0	0
T23	6402	3589	0	0
T24	5618	0	0	0
T25	9048	0	0	0
T28	3474	0	0	0
T49	0	2442	0	0
T51	0	3074	0	0
T128	4230	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390767546	390446968	0	0
T1	256846	256830	0	0
T2	2850	2712	0	0
T3	4376	4268	0	0
T4	48020	46820	0	0
T9	4490	4340	0	0
T10	6540	6420	0	0
T11	10916	10756	0	0
T23	6402	6274	0	0
T24	5618	5502	0	0
T25	9048	8872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390767546	390446968	0	0
T1	256846	256830	0	0
T2	2850	2712	0	0
T3	4376	4268	0	0
T4	48020	46820	0	0
T9	4490	4340	0	0
T10	6540	6420	0	0
T11	10916	10756	0	0
T23	6402	6274	0	0
T24	5618	5502	0	0
T25	9048	8872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390767546	390446968	0	0
T1	256846	256830	0	0
T2	2850	2712	0	0
T3	4376	4268	0	0
T4	48020	46820	0	0
T9	4490	4340	0	0
T10	6540	6420	0	0
T11	10916	10756	0	0
T23	6402	6274	0	0
T24	5618	5502	0	0
T25	9048	8872	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	390487844	1128980	0	0
T4	48020	0	0	0
T5	16146	0	0	0
T6	0	1447	0	0
T9	4490	2766	0	0
T10	6540	5162	0	0
T11	10916	8031	0	0
T12	0	1678	0	0
T15	0	254	0	0
T21	0	2464	0	0
T22	0	7174	0	0
T23	6402	3589	0	0
T24	5618	0	0	0
T25	9048	0	0	0
T28	3474	0	0	0
T51	0	3074	0	0
T128	4230	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T51,T156
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T117
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T122,T123,T124
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	195061737	513897	0	0
DepthKnown_A	195383773	195223484	0	0
RvalidKnown_A	195383773	195223484	0	0
WreadyKnown_A	195383773	195223484	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	195243922	558652	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195061737	513897	0	0
T4	24010	0	0	0
T5	8073	0	0	0
T6	0	97	0	0
T9	2245	1369	0	0
T10	3270	2525	0	0
T11	5458	4009	0	0
T12	0	812	0	0
T21	0	1221	0	0
T22	0	3532	0	0
T23	3201	1739	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T28	1737	0	0	0
T49	0	1162	0	0
T51	0	1500	0	0
T128	2115	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	195243922	558652	0	0
T4	24010	0	0	0
T5	8073	0	0	0
T6	0	714	0	0
T9	2245	1369	0	0
T10	3270	2525	0	0
T11	5458	4009	0	0
T12	0	812	0	0
T15	0	128	0	0
T21	0	1221	0	0
T22	0	3532	0	0
T23	3201	1739	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T28	1737	0	0	0
T51	0	1500	0	0
T128	2115	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T120
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T157,T158
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	195061737	525225	0	0
DepthKnown_A	195383773	195223484	0	0
RvalidKnown_A	195383773	195223484	0	0
WreadyKnown_A	195383773	195223484	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	195243922	570328	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195061737	525225	0	0
T4	24010	0	0	0
T5	8073	0	0	0
T6	0	84	0	0
T9	2245	1397	0	0
T10	3270	2637	0	0
T11	5458	4022	0	0
T12	0	866	0	0
T21	0	1243	0	0
T22	0	3642	0	0
T23	3201	1850	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T28	1737	0	0	0
T49	0	1280	0	0
T51	0	1574	0	0
T128	2115	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	195243922	570328	0	0
T4	24010	0	0	0
T5	8073	0	0	0
T6	0	733	0	0
T9	2245	1397	0	0
T10	3270	2637	0	0
T11	5458	4022	0	0
T12	0	866	0	0
T15	0	126	0	0
T21	0	1243	0	0
T22	0	3642	0	0
T23	3201	1850	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T28	1737	0	0	0
T51	0	1574	0	0
T128	2115	0	0	0