Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 100.00 95.24 85.71 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 100.00 95.24 85.71 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
SCORELINE
95.24 100.00
tb.dut.u_edn_core.u_prim_packer_fifo_cs

Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1


Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
SCORECOND
95.24 95.24
tb.dut.u_edn_core.u_prim_packer_fifo_cs

TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT9,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T10,T11
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T10,T23
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T34
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 1563070184 176014665 0 6520
ValidOPairedWithReadyI_A 1563070184 176014665 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1563070184 176014665 0 6520
T1 128423 124648 0 1
T2 1425 801 0 1
T3 2188 1368 0 1
T4 96040 11080 0 4
T5 40365 1544 0 5
T6 3372 0 0 2
T9 4490 681 0 2
T10 13080 1032 0 4
T11 21832 2349 0 4
T15 2792 0 0 4
T16 2122 0 0 1
T17 0 1093 0 0
T22 0 966 0 0
T23 19206 0 0 6
T24 11236 2035 0 4
T25 18096 2772 0 4
T28 8685 1094 0 5
T106 2252 1004 0 2
T109 7419 3391 0 3
T110 5535 1211 0 3
T111 4275 1104 0 3
T112 1124 0 0 1
T127 0 3647 0 0
T128 10575 0 0 5
T129 0 2244 0 0
T130 0 434982 0 0
T131 0 2362 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1563070184 176014665 0 0
T1 128423 124648 0 0
T2 1425 801 0 0
T3 2188 1368 0 0
T4 96040 11080 0 0
T5 40365 1544 0 0
T6 3372 0 0 0
T9 4490 681 0 0
T10 13080 1032 0 0
T11 21832 2349 0 0
T15 2792 0 0 0
T16 2122 0 0 0
T17 0 1093 0 0
T22 0 966 0 0
T23 19206 0 0 0
T24 11236 2035 0 0
T25 18096 2772 0 0
T28 8685 1094 0 0
T106 2252 1004 0 0
T109 7419 3391 0 0
T110 5535 1211 0 0
T111 4275 1104 0 0
T112 1124 0 0 0
T127 0 3647 0 0
T128 10575 0 0 0
T129 0 2244 0 0
T130 0 434982 0 0
T131 0 2362 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT9,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T10,T11
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T10,T23
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Line No.TotalCoveredPercent
Branches 14 12 85.71
TERNARY 142 4 3 75.00
TERNARY 147 3 2 66.67
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 195383773 121823 0 815
ValidOPairedWithReadyI_A 195383773 121823 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 121823 0 815
T4 24010 0 0 1
T5 8073 0 0 1
T9 2245 460 0 1
T10 3270 756 0 1
T11 5458 514 0 1
T16 0 42 0 0
T17 0 42 0 0
T21 0 731 0 0
T23 3201 718 0 1
T24 2809 0 0 1
T25 4524 18 0 1
T28 1737 0 0 1
T109 0 11 0 0
T110 0 68 0 0
T128 2115 0 0 1

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 121823 0 0
T4 24010 0 0 0
T5 8073 0 0 0
T9 2245 460 0 0
T10 3270 756 0 0
T11 5458 514 0 0
T16 0 42 0 0
T17 0 42 0 0
T21 0 731 0 0
T23 3201 718 0 0
T24 2809 0 0 0
T25 4524 18 0 0
T28 1737 0 0 0
T109 0 11 0 0
T110 0 68 0 0
T128 2115 0 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T74
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 195383773 174381081 0 815
ValidOPairedWithReadyI_A 195383773 174381081 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 174381081 0 815
T1 128423 124648 0 1
T2 1425 801 0 1
T3 2188 1368 0 1
T4 24010 11080 0 1
T5 0 1544 0 0
T9 2245 0 0 1
T10 3270 0 0 1
T11 5458 2349 0 1
T23 3201 0 0 1
T24 2809 2035 0 1
T25 4524 0 0 1
T28 0 1094 0 0
T110 0 1211 0 0
T111 0 1104 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 174381081 0 0
T1 128423 124648 0 0
T2 1425 801 0 0
T3 2188 1368 0 0
T4 24010 11080 0 0
T5 0 1544 0 0
T9 2245 0 0 0
T10 3270 0 0 0
T11 5458 2349 0 0
T23 3201 0 0 0
T24 2809 2035 0 0
T25 4524 0 0 0
T28 0 1094 0 0
T110 0 1211 0 0
T111 0 1104 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9,T25,T106

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT9,T25,T106
10CoveredT9,T25,T106
11CoveredT9,T25,T106

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T25,T106

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT9,T25,T106

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT9,T25,T106
11CoveredT9,T25,T106

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T25,T106

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T25,T106

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T25,T106

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T25,T106

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT9,T25,T106
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT70,T71,T197
11CoveredT9,T25,T106

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT9,T25,T106
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T9,T25,T106
0 0 1 Covered T9,T25,T106
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T25,T106
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T25,T106
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 195383773 444044 0 815
ValidOPairedWithReadyI_A 195383773 444044 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 444044 0 815
T4 24010 0 0 1
T5 8073 0 0 1
T9 2245 681 0 1
T10 3270 0 0 1
T11 5458 0 0 1
T17 0 1093 0 0
T22 0 966 0 0
T23 3201 0 0 1
T24 2809 0 0 1
T25 4524 2772 0 1
T28 1737 0 0 1
T106 0 1004 0 0
T109 0 1705 0 0
T127 0 2343 0 0
T128 2115 0 0 1
T129 0 2244 0 0
T130 0 217224 0 0
T131 0 1489 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 444044 0 0
T4 24010 0 0 0
T5 8073 0 0 0
T9 2245 681 0 0
T10 3270 0 0 0
T11 5458 0 0 0
T17 0 1093 0 0
T22 0 966 0 0
T23 3201 0 0 0
T24 2809 0 0 0
T25 4524 2772 0 0
T28 1737 0 0 0
T106 0 1004 0 0
T109 0 1705 0 0
T127 0 2343 0 0
T128 2115 0 0 0
T129 0 2244 0 0
T130 0 217224 0 0
T131 0 1489 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT109,T127,T49

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT109,T127,T49
10CoveredT10,T109,T127
11CoveredT109,T127,T49

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT109,T127,T49

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT10,T109,T127

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT10,T109,T127
11CoveredT10,T109,T127

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T109,T127

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T109,T127

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T109,T127

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T109,T127

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT10,T109,T127
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT34,T65,T198
11CoveredT10,T109,T127

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT10,T109,T127
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T10,T109,T127
0 0 1 Covered T10,T109,T127
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T10,T109,T127
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T10,T109,T127
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 195383773 419970 0 815
ValidOPairedWithReadyI_A 195383773 419970 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 419970 0 815
T4 24010 0 0 1
T5 8073 0 0 1
T10 3270 1032 0 1
T11 5458 0 0 1
T13 0 652 0 0
T15 698 0 0 1
T23 3201 0 0 1
T24 2809 0 0 1
T25 4524 0 0 1
T28 1737 0 0 1
T34 0 126 0 0
T49 0 1291 0 0
T105 0 1145 0 0
T109 0 1686 0 0
T127 0 1304 0 0
T128 2115 0 0 1
T130 0 217758 0 0
T131 0 873 0 0
T132 0 2679 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 419970 0 0
T4 24010 0 0 0
T5 8073 0 0 0
T10 3270 1032 0 0
T11 5458 0 0 0
T13 0 652 0 0
T15 698 0 0 0
T23 3201 0 0 0
T24 2809 0 0 0
T25 4524 0 0 0
T28 1737 0 0 0
T34 0 126 0 0
T49 0 1291 0 0
T105 0 1145 0 0
T109 0 1686 0 0
T127 0 1304 0 0
T128 2115 0 0 0
T130 0 217758 0 0
T131 0 873 0 0
T132 0 2679 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10,T25,T128

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT10,T25,T128
10CoveredT10,T25,T128
11CoveredT10,T25,T128

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T25,T128

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT10,T25,T128

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT10,T25,T128
11CoveredT10,T25,T128

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T25,T128

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T25,T128

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T25,T128

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T25,T128

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT10,T25,T128
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT166,T199,T200
11CoveredT10,T25,T128

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT10,T25,T128
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T10,T25,T128
0 0 1 Covered T10,T25,T128
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T10,T25,T128
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T10,T25,T128
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 195383773 191574 0 815
ValidOPairedWithReadyI_A 195383773 191574 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 191574 0 815
T4 24010 0 0 1
T5 8073 0 0 1
T10 3270 946 0 1
T11 5458 0 0 1
T15 698 0 0 1
T23 3201 0 0 1
T24 2809 0 0 1
T25 4524 2704 0 1
T28 1737 0 0 1
T49 0 937 0 0
T53 0 777 0 0
T109 0 1618 0 0
T127 0 1764 0 0
T128 2115 1650 0 1
T132 0 2879 0 0
T134 0 1573 0 0
T147 0 2485 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 191574 0 0
T4 24010 0 0 0
T5 8073 0 0 0
T10 3270 946 0 0
T11 5458 0 0 0
T15 698 0 0 0
T23 3201 0 0 0
T24 2809 0 0 0
T25 4524 2704 0 0
T28 1737 0 0 0
T49 0 937 0 0
T53 0 777 0 0
T109 0 1618 0 0
T127 0 1764 0 0
T128 2115 1650 0 0
T132 0 2879 0 0
T134 0 1573 0 0
T147 0 2485 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT127,T49,T132

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT127,T49,T132
10CoveredT23,T127,T49
11CoveredT127,T49,T132

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT127,T49,T132

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T127,T49

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT23,T127,T49
11CoveredT23,T127,T49

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T127,T49

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T127,T49

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T127,T49

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T127,T49

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT23,T127,T49
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT201,T98,T202
11CoveredT23,T127,T49

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT23,T127,T49
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T23,T127,T49
0 0 1 Covered T23,T127,T49
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T23,T127,T49
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T23,T127,T49
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 195383773 164779 0 815
ValidOPairedWithReadyI_A 195383773 164779 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 164779 0 815
T5 8073 0 0 1
T6 1686 0 0 1
T15 698 0 0 1
T23 3201 1311 0 1
T28 1737 0 0 1
T49 0 1081 0 0
T106 1126 0 0 1
T109 2473 0 0 1
T110 1845 0 0 1
T111 1425 0 0 1
T127 0 1573 0 0
T128 2115 0 0 1
T132 0 2760 0 0
T133 0 2098 0 0
T134 0 1743 0 0
T135 0 1811 0 0
T147 0 2456 0 0
T149 0 1461 0 0
T150 0 2592 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 164779 0 0
T5 8073 0 0 0
T6 1686 0 0 0
T15 698 0 0 0
T23 3201 1311 0 0
T28 1737 0 0 0
T49 0 1081 0 0
T106 1126 0 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T127 0 1573 0 0
T128 2115 0 0 0
T132 0 2760 0 0
T133 0 2098 0 0
T134 0 1743 0 0
T135 0 1811 0 0
T147 0 2456 0 0
T149 0 1461 0 0
T150 0 2592 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT23,T29,T127

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT23,T29,T127
10CoveredT23,T29,T127
11CoveredT23,T29,T127

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T29,T127

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T29,T127

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT23,T29,T127
11CoveredT23,T29,T127

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T29,T127

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T29,T127

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T29,T127

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T29,T127

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT23,T29,T127
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT73,T66,T203
11CoveredT23,T29,T127

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT23,T29,T127
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T23,T29,T127
0 0 1 Covered T23,T29,T127
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T23,T29,T127
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T23,T29,T127
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 195383773 142725 0 815
ValidOPairedWithReadyI_A 195383773 142725 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 142725 0 815
T5 8073 0 0 1
T6 1686 0 0 1
T15 698 0 0 1
T23 3201 1277 0 1
T28 1737 0 0 1
T29 0 1224 0 0
T41 0 645 0 0
T49 0 1075 0 0
T51 0 1229 0 0
T56 0 766 0 0
T60 0 862 0 0
T90 0 673 0 0
T106 1126 0 0 1
T109 2473 0 0 1
T110 1845 0 0 1
T111 1425 0 0 1
T127 0 1564 0 0
T128 2115 0 0 1
T132 0 2268 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 142725 0 0
T5 8073 0 0 0
T6 1686 0 0 0
T15 698 0 0 0
T23 3201 1277 0 0
T28 1737 0 0 0
T29 0 1224 0 0
T41 0 645 0 0
T49 0 1075 0 0
T51 0 1229 0 0
T56 0 766 0 0
T60 0 862 0 0
T90 0 673 0 0
T106 1126 0 0 0
T109 2473 0 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T127 0 1564 0 0
T128 2115 0 0 0
T132 0 2268 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
94 1 1
96 1 1
127 1 1
128 1 1
130 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
147 1 1
151 1 1
156 1 1
157 1 1
158 1 1
163 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT109,T21,T127

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT109,T21,T127
10CoveredT109,T21,T22
11CoveredT109,T21,T127

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT109,T21,T127

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT109,T21,T22

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT109,T21,T22
11CoveredT109,T21,T22

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT109,T21,T22

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT109,T21,T22

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT109,T21,T22

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT109,T21,T22

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT109,T21,T22
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT26,T75,T72
11CoveredT109,T21,T22

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT109,T21,T22
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 142 (clear_status) ? -2-: 142 (load_data) ? -3-: 142 (gen_unpack_mode.pull_data) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T109,T21,T22
0 0 1 Covered T109,T21,T22
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 (clear_status) ? -2-: 147 (gen_unpack_mode.pull_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T109,T21,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 (clear_data) ? -2-: 151 (load_data) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T109,T21,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 82 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 195383773 148669 0 815
ValidOPairedWithReadyI_A 195383773 148669 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 148669 0 815
T16 2122 0 0 1
T17 2025 0 0 1
T21 1645 921 0 1
T22 4707 1027 0 1
T26 0 119 0 0
T29 1922 0 0 1
T34 0 1241 0 0
T109 2473 1635 0 1
T110 1845 0 0 1
T111 1425 0 0 1
T112 1124 0 0 1
T113 892 0 0 1
T127 0 1282 0 0
T132 0 2290 0 0
T135 0 1141 0 0
T147 0 2110 0 0
T151 0 1956 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195383773 148669 0 0
T16 2122 0 0 0
T17 2025 0 0 0
T21 1645 921 0 0
T22 4707 1027 0 0
T26 0 119 0 0
T29 1922 0 0 0
T34 0 1241 0 0
T109 2473 1635 0 0
T110 1845 0 0 0
T111 1425 0 0 0
T112 1124 0 0 0
T113 892 0 0 0
T127 0 1282 0 0
T132 0 2290 0 0
T135 0 1141 0 0
T147 0 2110 0 0
T151 0 1956 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%