Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	117	1			T23	1		T30	1		T94	1
auto_req_mode	140	1			T10	1		T9	1		T21	1
sw_mode	2945	1			T1	34		T3	1		T24	72

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

304

1

T3

1

T25

1

T27

1

single

96

1

T23

1

T114

1

T34

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1573	1			T1	34		T25	1		T26	9
auto[2]	31	1			T23	1		T10	1		T21	1
auto[3]	51	1			T260	1		T133	1		T204	15
auto[4]	291	1			T9	1		T11	1		T136	1
auto[5]	90	1			T128	6		T261	1		T262	1
auto[6]	115	1			T27	1		T138	1		T263	1
auto[7]	1051	1			T3	1		T24	72		T30	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	72	1			T94	1		T60	1		T264	1
auto[1]	auto_req_mode	83	1			T28	1		T33	1		T34	1
auto[1]	sw_mode	1418	1			T1	34		T25	1		T26	9
auto[2]	boot_req_mode	2	1			T23	1		T265	1		-	-
auto[2]	auto_req_mode	7	1			T10	1		T21	1		T22	1
auto[2]	sw_mode	22	1			T266	1		T267	1		T268	7
auto[3]	boot_req_mode	2	1			T269	1		T270	1		-	-
auto[3]	auto_req_mode	2	1			T271	1		T272	1		-	-
auto[3]	sw_mode	47	1			T260	1		T133	1		T204	15
auto[4]	boot_req_mode	3	1			T136	1		T273	1		T274	1
auto[4]	auto_req_mode	5	1			T9	1		T11	1		T275	1
auto[4]	sw_mode	283	1			T276	82		T277	16		T278	83
auto[5]	boot_req_mode	1	1			T261	1		-	-		-	-
auto[5]	auto_req_mode	4	1			T279	1		T280	1		T281	1
auto[5]	sw_mode	85	1			T128	6		T262	1		T195	69
auto[6]	boot_req_mode	8	1			T138	1		T282	1		T283	1
auto[6]	auto_req_mode	4	1			T263	1		T284	1		T285	1
auto[6]	sw_mode	103	1			T27	1		T196	85		T286	1
auto[7]	boot_req_mode	29	1			T30	1		T115	1		T117	1
auto[7]	auto_req_mode	35	1			T120	1		T121	1		T122	1
auto[7]	sw_mode	987	1			T3	1		T24	72		T113	1