Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2840	1			T1	28		T3	1		T23	1
non_zero_bins[1]	1956	1			T1	7		T3	2		T24	28
zero	8644	1			T1	89		T2	5		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	523	1			T1	7		T3	1		T24	7
uni	3740	1			T1	40		T3	1		T23	2
gen	4123	1			T1	34		T2	2		T3	1
res	856	1			T1	3		T23	1		T24	12
ins	4198	1			T1	40		T2	3		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8940

1

T1

91

T2

3

T3

2

mubi_true

4500

1

T1

33

T2

2

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

13440

1

T1

124

T2

5

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	115	1			T1	2		T24	2		T112	4
upd	non_zero_bins[0]	pass	mubi_true	131	1			T1	2		T24	2		T125	2
upd	non_zero_bins[1]	pass	mubi_false	95	1			T1	2		T3	1		T24	1
upd	non_zero_bins[1]	pass	mubi_true	79	1			T24	1		T30	1		T125	1
upd	zero	pass	mubi_false	53	1			T1	1		T26	1		T125	1
upd	zero	pass	mubi_true	50	1			T24	1		T131	1		T132	1
uni	zero	pass	mubi_false	2766	1			T1	29		T3	1		T23	2
uni	zero	pass	mubi_true	974	1			T1	11		T24	24		T27	1
gen	non_zero_bins[0]	pass	mubi_false	500	1			T1	5		T23	1		T24	8
gen	non_zero_bins[0]	pass	mubi_true	593	1			T1	5		T3	1		T24	9
gen	non_zero_bins[1]	pass	mubi_false	333	1			T1	1		T24	2		T25	1
gen	non_zero_bins[1]	pass	mubi_true	417	1			T1	2		T24	4		T26	1
gen	zero	pass	mubi_false	1843	1			T1	19		T2	1		T4	1
gen	zero	pass	mubi_true	437	1			T1	2		T2	1		T23	1
res	non_zero_bins[0]	pass	mubi_false	198	1			T1	1		T24	2		T26	2
res	non_zero_bins[0]	pass	mubi_true	201	1			T1	2		T24	4		T25	1
res	non_zero_bins[1]	pass	mubi_false	127	1			T24	2		T26	1		T10	2
res	non_zero_bins[1]	pass	mubi_true	140	1			T24	2		T112	1		T126	2
res	zero	pass	mubi_false	82	1			T24	1		T26	1		T8	1
res	zero	pass	mubi_true	108	1			T23	1		T24	1		T112	1
ins	non_zero_bins[0]	pass	mubi_false	550	1			T1	6		T24	10		T112	5
ins	non_zero_bins[0]	pass	mubi_true	552	1			T1	5		T24	12		T26	3
ins	non_zero_bins[1]	pass	mubi_false	361	1			T1	1		T24	7		T25	1
ins	non_zero_bins[1]	pass	mubi_true	404	1			T1	1		T3	1		T24	9
ins	zero	pass	mubi_false	1917	1			T1	24		T2	2		T23	1
ins	zero	pass	mubi_true	414	1			T1	3		T2	1		T4	3

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded