Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T23,T24
DataWait	75	Covered	T1,T4,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T18
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T156,T157,T158
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T23,T24
DataWait->AckPls	80	Covered	T1,T23,T24
DataWait->Disabled	107	Covered	T159,T160,T53
DataWait->Error	99	Covered	T4,T5,T101
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T19,T20
EndPointClear->Disabled	107	Covered	T161,T82,T83
EndPointClear->Error	99	Covered	T13,T79,T80
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T4,T23
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T2,T4,T18

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T23,T24
Idle	-	1	0	-	Covered	T1,T4,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T23,T24
DataWait	-	-	-	0	Covered	T1,T4,T23
AckPls	-	-	-	-	Covered	T1,T23,T24
Error	-	-	-	-	Covered	T2,T4,T18
default	-	-	-	-	Covered	T18,T98,T13

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T18
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1405246220	1110218	0	0
FpvSecCmErrorStEscalate_A	1405246220	1119339	0	0
u_state_regs_A	1405205043	1403894055	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1405246220	1110218	0	0
T2	15134	4431	0	0
T3	31052	0	0	0
T4	6342	3213	0	0
T5	0	2863	0	0
T13	0	49847	0	0
T14	0	2800	0	0
T15	0	8078	0	0
T18	7532	4220	0	0
T23	9562	0	0	0
T24	2002987	0	0	0
T25	14350	0	0	0
T26	209552	0	0	0
T27	29064	0	0	0
T79	0	1980	0	0
T98	0	7636	0	0
T101	0	2765	0	0
T102	12082	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1405246220	1119339	0	0
T2	15134	4438	0	0
T3	31052	0	0	0
T4	6342	3220	0	0
T5	0	2870	0	0
T13	0	50757	0	0
T14	0	2807	0	0
T15	0	8085	0	0
T18	7532	4227	0	0
T23	9562	0	0	0
T24	2002987	0	0	0
T25	14350	0	0	0
T26	209552	0	0	0
T27	29064	0	0	0
T79	0	1987	0	0
T98	0	7643	0	0
T101	0	2772	0	0
T102	12082	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1405205043	1403894055	0	0
T1	939288	939218	0	0
T2	13976	12905	0	0
T3	31052	30646	0	0
T4	6162	5091	0	0
T18	7393	6511	0	0
T23	9562	9135	0	0
T24	2002987	2002910	0	0
T25	14350	13678	0	0
T26	209552	206087	0	0
T27	29064	28455	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T27,T8,T106
DataWait	75	Covered	T27,T8,T106
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T18
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T27,T8,T106
DataWait->AckPls	80	Covered	T27,T8,T106
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T162,T163,T164
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T19,T20
EndPointClear->Disabled	107	Covered	T161,T82,T83
EndPointClear->Error	99	Covered	T13,T79,T80
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T27,T8,T106
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T2,T4,T18

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T27,T8,T106
Idle	-	1	0	-	Covered	T27,T8,T106
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T27,T8,T106
DataWait	-	-	-	0	Covered	T27,T8,T114
AckPls	-	-	-	-	Covered	T27,T8,T106
Error	-	-	-	-	Covered	T2,T4,T18
default	-	-	-	-	Covered	T13,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T18
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200749460	158874	0	0
FpvSecCmErrorStEscalate_A	200749460	160177	0	0
u_state_regs_A	200749460	200562176	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	158874	0	0
T2	2162	633	0	0
T3	4436	0	0	0
T4	906	459	0	0
T5	0	409	0	0
T13	0	7121	0	0
T14	0	400	0	0
T15	0	1154	0	0
T18	1076	610	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	290	0	0
T98	0	1098	0	0
T101	0	395	0	0
T102	1726	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	160177	0	0
T2	2162	634	0	0
T3	4436	0	0	0
T4	906	460	0	0
T5	0	410	0	0
T13	0	7251	0	0
T14	0	401	0	0
T15	0	1155	0	0
T18	1076	611	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	291	0	0
T98	0	1099	0	0
T101	0	396	0	0
T102	1726	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T23,T24
DataWait	75	Covered	T1,T4,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T18
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T23,T24
DataWait->AckPls	80	Covered	T1,T23,T24
DataWait->Disabled	107	Covered	T160,T165,T166
DataWait->Error	99	Covered	T4,T5,T101
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T19,T20
EndPointClear->Disabled	107	Covered	T161,T82,T83
EndPointClear->Error	99	Covered	T13,T6,T167
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T4,T23
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T2,T14,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T23,T24
Idle	-	1	0	-	Covered	T1,T4,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T23,T24
DataWait	-	-	-	0	Covered	T1,T4,T23
AckPls	-	-	-	-	Covered	T1,T23,T24
Error	-	-	-	-	Covered	T2,T4,T18
default	-	-	-	-	Covered	T18,T98,T13

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T18
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200749460	156974	0	0
FpvSecCmErrorStEscalate_A	200749460	158277	0	0
u_state_regs_A	200708283	200520999	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	156974	0	0
T2	2162	633	0	0
T3	4436	0	0	0
T4	906	459	0	0
T5	0	409	0	0
T13	0	7121	0	0
T14	0	400	0	0
T15	0	1154	0	0
T18	1076	560	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	240	0	0
T98	0	1048	0	0
T101	0	395	0	0
T102	1726	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	158277	0	0
T2	2162	634	0	0
T3	4436	0	0	0
T4	906	460	0	0
T5	0	410	0	0
T13	0	7251	0	0
T14	0	401	0	0
T15	0	1155	0	0
T18	1076	561	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	241	0	0
T98	0	1049	0	0
T101	0	396	0	0
T102	1726	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200708283	200520999	0	0
T1	134184	134174	0	0
T2	1004	851	0	0
T3	4436	4378	0	0
T4	726	573	0	0
T18	937	811	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T27,T30,T60
DataWait	75	Covered	T27,T30,T60
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T18
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T27,T30,T60
DataWait->AckPls	80	Covered	T27,T30,T60
DataWait->Disabled	107	Covered	T38,T168,T169
DataWait->Error	99	Covered	T64,T100,T170
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T19,T20
EndPointClear->Disabled	107	Covered	T161,T82,T83
EndPointClear->Error	99	Covered	T13,T79,T80
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T27,T30,T60
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T2,T4,T18

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T27,T30,T60
Idle	-	1	0	-	Covered	T27,T30,T60
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T27,T30,T60
DataWait	-	-	-	0	Covered	T27,T30,T60
AckPls	-	-	-	-	Covered	T27,T30,T60
Error	-	-	-	-	Covered	T2,T4,T18
default	-	-	-	-	Covered	T13,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T18
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200749460	158874	0	0
FpvSecCmErrorStEscalate_A	200749460	160177	0	0
u_state_regs_A	200749460	200562176	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	158874	0	0
T2	2162	633	0	0
T3	4436	0	0	0
T4	906	459	0	0
T5	0	409	0	0
T13	0	7121	0	0
T14	0	400	0	0
T15	0	1154	0	0
T18	1076	610	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	290	0	0
T98	0	1098	0	0
T101	0	395	0	0
T102	1726	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	160177	0	0
T2	2162	634	0	0
T3	4436	0	0	0
T4	906	460	0	0
T5	0	410	0	0
T13	0	7251	0	0
T14	0	401	0	0
T15	0	1155	0	0
T18	1076	611	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	291	0	0
T98	0	1099	0	0
T101	0	396	0	0
T102	1726	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T30,T29,T115
DataWait	75	Covered	T30,T29,T115
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T18
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T30,T29,T115
DataWait->AckPls	80	Covered	T30,T29,T115
DataWait->Disabled	107	Covered	T28,T171,T39
DataWait->Error	99	Covered	T172,T91,T173
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T19,T20
EndPointClear->Disabled	107	Covered	T161,T82,T83
EndPointClear->Error	99	Covered	T13,T79,T80
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T30,T29,T115
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T2,T4,T18

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T30,T29,T115
Idle	-	1	0	-	Covered	T30,T29,T115
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T30,T29,T115
DataWait	-	-	-	0	Covered	T30,T29,T115
AckPls	-	-	-	-	Covered	T30,T29,T115
Error	-	-	-	-	Covered	T2,T4,T18
default	-	-	-	-	Covered	T13,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T18
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200749460	158874	0	0
FpvSecCmErrorStEscalate_A	200749460	160177	0	0
u_state_regs_A	200749460	200562176	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	158874	0	0
T2	2162	633	0	0
T3	4436	0	0	0
T4	906	459	0	0
T5	0	409	0	0
T13	0	7121	0	0
T14	0	400	0	0
T15	0	1154	0	0
T18	1076	610	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	290	0	0
T98	0	1098	0	0
T101	0	395	0	0
T102	1726	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	160177	0	0
T2	2162	634	0	0
T3	4436	0	0	0
T4	906	460	0	0
T5	0	410	0	0
T13	0	7251	0	0
T14	0	401	0	0
T15	0	1155	0	0
T18	1076	611	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	291	0	0
T98	0	1099	0	0
T101	0	396	0	0
T102	1726	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T27,T8
DataWait	75	Covered	T23,T27,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T18
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T158
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T27,T8
DataWait->AckPls	80	Covered	T23,T27,T8
DataWait->Disabled	107	Covered	T159,T55,T174
DataWait->Error	99	Covered	T44,T175,T176
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T19,T20
EndPointClear->Disabled	107	Covered	T161,T82,T83
EndPointClear->Error	99	Covered	T13,T79,T80
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T27,T8
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T2,T4,T18

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T27,T8
Idle	-	1	0	-	Covered	T23,T27,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T27,T8
DataWait	-	-	-	0	Covered	T23,T27,T113
AckPls	-	-	-	-	Covered	T23,T27,T8
Error	-	-	-	-	Covered	T2,T4,T18
default	-	-	-	-	Covered	T13,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T18
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200749460	158874	0	0
FpvSecCmErrorStEscalate_A	200749460	160177	0	0
u_state_regs_A	200749460	200562176	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	158874	0	0
T2	2162	633	0	0
T3	4436	0	0	0
T4	906	459	0	0
T5	0	409	0	0
T13	0	7121	0	0
T14	0	400	0	0
T15	0	1154	0	0
T18	1076	610	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	290	0	0
T98	0	1098	0	0
T101	0	395	0	0
T102	1726	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	160177	0	0
T2	2162	634	0	0
T3	4436	0	0	0
T4	906	460	0	0
T5	0	410	0	0
T13	0	7251	0	0
T14	0	401	0	0
T15	0	1155	0	0
T18	1076	611	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	291	0	0
T98	0	1099	0	0
T101	0	396	0	0
T102	1726	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T30,T114
DataWait	75	Covered	T2,T3,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T18
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T157
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T30,T114
DataWait->AckPls	80	Covered	T3,T30,T114
DataWait->Disabled	107	Covered	T53,T177,T178
DataWait->Error	99	Covered	T2,T14,T59
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T19,T20
EndPointClear->Disabled	107	Covered	T161,T82,T83
EndPointClear->Error	99	Covered	T13,T79,T80
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T30
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T4,T18,T98

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T30,T114
Idle	-	1	0	-	Covered	T2,T3,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T30,T114
DataWait	-	-	-	0	Covered	T2,T3,T114
AckPls	-	-	-	-	Covered	T3,T30,T114
Error	-	-	-	-	Covered	T2,T4,T18
default	-	-	-	-	Covered	T13,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T18
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200749460	158874	0	0
FpvSecCmErrorStEscalate_A	200749460	160177	0	0
u_state_regs_A	200749460	200562176	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	158874	0	0
T2	2162	633	0	0
T3	4436	0	0	0
T4	906	459	0	0
T5	0	409	0	0
T13	0	7121	0	0
T14	0	400	0	0
T15	0	1154	0	0
T18	1076	610	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	290	0	0
T98	0	1098	0	0
T101	0	395	0	0
T102	1726	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	160177	0	0
T2	2162	634	0	0
T3	4436	0	0	0
T4	906	460	0	0
T5	0	410	0	0
T13	0	7251	0	0
T14	0	401	0	0
T15	0	1155	0	0
T18	1076	611	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	291	0	0
T98	0	1099	0	0
T101	0	396	0	0
T102	1726	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T30,T113,T114
DataWait	75	Covered	T30,T113,T114
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T18
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T156
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T30,T113,T114
DataWait->AckPls	80	Covered	T30,T113,T114
DataWait->Disabled	107	Covered	T54,T179,T180
DataWait->Error	99	Covered	T181,T32
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T19,T20
EndPointClear->Disabled	107	Covered	T161,T82,T83
EndPointClear->Error	99	Covered	T13,T79,T80
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T30,T113,T114
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T2,T4,T18

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T30,T113,T114
Idle	-	1	0	-	Covered	T30,T113,T114
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T30,T113,T114
DataWait	-	-	-	0	Covered	T30,T113,T114
AckPls	-	-	-	-	Covered	T30,T113,T114
Error	-	-	-	-	Covered	T2,T4,T18
default	-	-	-	-	Covered	T13,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T18
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200749460	158874	0	0
FpvSecCmErrorStEscalate_A	200749460	160177	0	0
u_state_regs_A	200749460	200562176	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	158874	0	0
T2	2162	633	0	0
T3	4436	0	0	0
T4	906	459	0	0
T5	0	409	0	0
T13	0	7121	0	0
T14	0	400	0	0
T15	0	1154	0	0
T18	1076	610	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	290	0	0
T98	0	1098	0	0
T101	0	395	0	0
T102	1726	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	160177	0	0
T2	2162	634	0	0
T3	4436	0	0	0
T4	906	460	0	0
T5	0	410	0	0
T13	0	7251	0	0
T14	0	401	0	0
T15	0	1155	0	0
T18	1076	611	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	291	0	0
T98	0	1099	0	0
T101	0	396	0	0
T102	1726	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0