Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T110,T108,T111
1	0	1	Covered	T2,T4,T18
1	1	0	Not Covered
1	1	1	Covered	T8,T10,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400620236	981560	0	0
DepthKnown_A	401498920	401124352	0	0
RvalidKnown_A	401498920	401124352	0	0
WreadyKnown_A	401498920	401124352	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	400981810	1070915	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400620236	981560	0	0
T5	0	228	0	0
T8	5274	639	0	0
T9	0	5167	0	0
T10	0	1537	0	0
T11	0	2415	0	0
T16	5218	95	0	0
T17	752	0	0	0
T21	0	1217	0	0
T28	0	6368	0	0
T30	5178	0	0	0
T33	0	2459	0	0
T34	0	3647	0	0
T60	2264	0	0	0
T94	4434	0	0	0
T98	814	0	0	0
T103	3676	0	0	0
T106	660	0	0	0
T112	593208	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401498920	401124352	0	0
T1	268368	268348	0	0
T2	4324	4018	0	0
T3	8872	8756	0	0
T4	1812	1506	0	0
T18	2152	1900	0	0
T23	2732	2610	0	0
T24	572282	572260	0	0
T25	4100	3908	0	0
T26	59872	58882	0	0
T27	8304	8130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401498920	401124352	0	0
T1	268368	268348	0	0
T2	4324	4018	0	0
T3	8872	8756	0	0
T4	1812	1506	0	0
T18	2152	1900	0	0
T23	2732	2610	0	0
T24	572282	572260	0	0
T25	4100	3908	0	0
T26	59872	58882	0	0
T27	8304	8130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401498920	401124352	0	0
T1	268368	268348	0	0
T2	4324	4018	0	0
T3	8872	8756	0	0
T4	1812	1506	0	0
T18	2152	1900	0	0
T23	2732	2610	0	0
T24	572282	572260	0	0
T25	4100	3908	0	0
T26	59872	58882	0	0
T27	8304	8130	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	400981810	1070915	0	0
T2	4324	2248	0	0
T3	8872	0	0	0
T4	1812	289	0	0
T5	0	3042	0	0
T8	0	639	0	0
T9	0	5167	0	0
T10	0	1537	0	0
T16	0	95	0	0
T17	0	24	0	0
T18	2152	258	0	0
T21	0	1217	0	0
T23	2732	0	0	0
T24	572282	0	0	0
T25	4100	0	0	0
T26	59872	0	0	0
T27	8304	0	0	0
T79	0	109	0	0
T102	3452	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T108,T143
1	0	1	Covered	T2,T4,T18
1	1	0	Not Covered
1	1	1	Covered	T8,T10,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	200310118	495519	0	0
DepthKnown_A	200749460	200562176	0	0
RvalidKnown_A	200749460	200562176	0	0
WreadyKnown_A	200749460	200562176	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	200490905	540367	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200310118	495519	0	0
T5	0	118	0	0
T8	2637	316	0	0
T9	0	2597	0	0
T10	0	761	0	0
T11	0	1208	0	0
T16	2609	52	0	0
T17	376	0	0	0
T21	0	617	0	0
T28	0	3273	0	0
T30	2589	0	0	0
T33	0	1246	0	0
T34	0	1910	0	0
T60	1132	0	0	0
T94	2217	0	0	0
T98	407	0	0	0
T103	1838	0	0	0
T106	330	0	0	0
T112	296604	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	200490905	540367	0	0
T2	2162	1119	0	0
T3	4436	0	0	0
T4	906	142	0	0
T5	0	1524	0	0
T8	0	316	0	0
T9	0	2597	0	0
T10	0	761	0	0
T16	0	52	0	0
T18	1076	128	0	0
T21	0	617	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	109	0	0
T102	1726	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T11,T144
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T110,T111,T145
1	0	1	Covered	T2,T4,T18
1	1	0	Not Covered
1	1	1	Covered	T8,T10,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	200310118	486041	0	0
DepthKnown_A	200749460	200562176	0	0
RvalidKnown_A	200749460	200562176	0	0
WreadyKnown_A	200749460	200562176	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	200490905	530548	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200310118	486041	0	0
T5	0	110	0	0
T8	2637	323	0	0
T9	0	2570	0	0
T10	0	776	0	0
T11	0	1207	0	0
T16	2609	43	0	0
T17	376	0	0	0
T21	0	600	0	0
T28	0	3095	0	0
T30	2589	0	0	0
T33	0	1213	0	0
T34	0	1737	0	0
T60	1132	0	0	0
T94	2217	0	0	0
T98	407	0	0	0
T103	1838	0	0	0
T106	330	0	0	0
T112	296604	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	200490905	530548	0	0
T2	2162	1129	0	0
T3	4436	0	0	0
T4	906	147	0	0
T5	0	1518	0	0
T8	0	323	0	0
T9	0	2570	0	0
T10	0	776	0	0
T16	0	43	0	0
T17	0	24	0	0
T18	1076	130	0	0
T21	0	600	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T102	1726	0	0	0