| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[0].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[1].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[2].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[3].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[4].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[5].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[6].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 1710 | 1 | T2 | 1 | T3 | 1 | T20 | 1 | ||||
| auto[2] | 24948 | 1 | T2 | 12 | T3 | 1 | T20 | 36 | ||||
| auto[3] | 23993 | 1 | T2 | 12 | T3 | 1 | T20 | 36 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 152 | 1 | T20 | 1 | T7 | 1 | T8 | 1 | ||||
| auto[2] | 6211 | 1 | T1 | 1 | T20 | 20 | T7 | 4 | ||||
| auto[3] | 6194 | 1 | T20 | 20 | T7 | 4 | T8 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 129 | 1 | T20 | 1 | T117 | 1 | T118 | 1 | ||||
| auto[2] | 3861 | 1 | T20 | 21 | T117 | 6 | T118 | 17 | ||||
| auto[3] | 3849 | 1 | T20 | 21 | T117 | 6 | T118 | 17 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 129 | 1 | T20 | 1 | T7 | 1 | T26 | 1 | ||||
| auto[2] | 2319 | 1 | T20 | 25 | T7 | 4 | T26 | 4 | ||||
| auto[3] | 2313 | 1 | T20 | 25 | T7 | 4 | T26 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 119 | 1 | T20 | 1 | T25 | 1 | T8 | 1 | ||||
| auto[2] | 6785 | 1 | T20 | 4 | T25 | 4 | T8 | 16 | ||||
| auto[3] | 6782 | 1 | T20 | 4 | T25 | 4 | T8 | 16 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 100 | 1 | T20 | 1 | T24 | 1 | T26 | 2 | ||||
| auto[2] | 3955 | 1 | T20 | 4 | T24 | 4 | T26 | 5 | ||||
| auto[3] | 3949 | 1 | T20 | 4 | T24 | 4 | T26 | 5 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 101 | 1 | T8 | 1 | T117 | 1 | T118 | 1 | ||||
| auto[2] | 2908 | 1 | T8 | 35 | T117 | 4 | T118 | 4 | ||||
| auto[3] | 2905 | 1 | T8 | 35 | T117 | 4 | T118 | 4 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |