Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	699681	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5913650

1

T1

67

T2

29

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1724408	1			T1	5		T2	42		T3	21
values[0x0]	2256995	1			T1	36		T2	15		T3	8
values[0x1]	2631928	1			T1	37		T2	14		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	337795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6275536

1

T1

70

T2

44

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27443	1			T103	1		T104	263		T160	1
valid_sources[0x01]	24459	1			T4	3		T103	2		T104	345
valid_sources[0x02]	25060	1			T22	8		T6	2		T104	301
valid_sources[0x03]	26114	1			T1	1		T4	1		T153	1
valid_sources[0x04]	25688	1			T4	4		T103	4		T104	340
valid_sources[0x05]	27652	1			T4	5		T145	97		T153	1
valid_sources[0x06]	24934	1			T1	1		T4	12		T103	7
valid_sources[0x07]	25960	1			T103	6		T104	306		T105	1
valid_sources[0x08]	24793	1			T4	10		T103	1		T104	330
valid_sources[0x09]	25533	1			T4	2		T103	2		T127	1
valid_sources[0x0a]	28351	1			T4	12		T103	2		T26	1
valid_sources[0x0b]	26303	1			T1	1		T103	1		T26	3
valid_sources[0x0c]	26010	1			T1	1		T103	5		T104	299
valid_sources[0x0d]	24540	1			T1	1		T4	1		T103	4
valid_sources[0x0e]	24691	1			T103	1		T104	302		T115	204
valid_sources[0x0f]	24730	1			T1	1		T103	1		T104	295
valid_sources[0x10]	25221	1			T4	7		T7	2		T11	1
valid_sources[0x11]	25756	1			T4	21		T103	1		T26	2
valid_sources[0x12]	27438	1			T7	2		T6	1		T104	300
valid_sources[0x13]	27393	1			T1	1		T103	1		T104	348
valid_sources[0x14]	24604	1			T26	1		T127	2		T104	293
valid_sources[0x15]	24879	1			T103	1		T26	1		T104	308
valid_sources[0x16]	26069	1			T1	1		T103	1		T104	304
valid_sources[0x17]	23780	1			T103	1		T104	280		T105	1
valid_sources[0x18]	24617	1			T4	6		T103	1		T26	2
valid_sources[0x19]	25874	1			T1	1		T23	2		T103	1
valid_sources[0x1a]	27005	1			T4	5		T146	1		T104	313
valid_sources[0x1b]	24988	1			T1	1		T103	1		T6	1
valid_sources[0x1c]	25784	1			T4	9		T103	4		T26	1
valid_sources[0x1d]	25223	1			T7	4		T127	2		T11	7
valid_sources[0x1e]	25538	1			T4	2		T22	1		T103	2
valid_sources[0x1f]	24886	1			T26	2		T11	6		T104	346
valid_sources[0x20]	27587	1			T104	322		T105	1		T161	2
valid_sources[0x21]	25159	1			T103	4		T11	1		T104	301
valid_sources[0x22]	24597	1			T4	14		T103	1		T104	312
valid_sources[0x23]	26817	1			T4	1		T103	2		T153	1
valid_sources[0x24]	25671	1			T7	4		T103	1		T26	3
valid_sources[0x25]	26023	1			T21	35		T7	8		T26	1
valid_sources[0x26]	25716	1			T4	5		T23	1		T26	1
valid_sources[0x27]	26440	1			T7	7		T26	1		T104	326
valid_sources[0x28]	27017	1			T4	6		T7	11		T103	1
valid_sources[0x29]	25437	1			T1	1		T7	3		T11	1
valid_sources[0x2a]	26510	1			T4	3		T23	1		T29	62
valid_sources[0x2b]	26298	1			T4	3		T103	2		T127	1
valid_sources[0x2c]	25594	1			T103	4		T104	327		T18	4
valid_sources[0x2d]	28998	1			T4	2		T26	2		T104	326
valid_sources[0x2e]	26171	1			T1	1		T103	1		T104	310
valid_sources[0x2f]	26323	1			T153	1		T104	328		T105	1
valid_sources[0x30]	25927	1			T1	2		T103	11		T104	285
valid_sources[0x31]	26118	1			T104	280		T117	9		T154	1
valid_sources[0x32]	24951	1			T103	2		T26	1		T11	1
valid_sources[0x33]	26433	1			T1	1		T7	12		T114	26
valid_sources[0x34]	25833	1			T104	304		T161	1		T115	198
valid_sources[0x35]	25971	1			T23	1		T153	1		T127	1
valid_sources[0x36]	26920	1			T4	2		T103	1		T104	316
valid_sources[0x37]	25434	1			T4	3		T103	7		T26	1
valid_sources[0x38]	27272	1			T103	4		T104	351		T18	1
valid_sources[0x39]	23763	1			T23	2		T103	4		T26	1
valid_sources[0x3a]	25136	1			T1	3		T6	2		T104	327
valid_sources[0x3b]	26790	1			T23	1		T103	3		T146	4
valid_sources[0x3c]	25392	1			T1	1		T103	3		T104	344
valid_sources[0x3d]	24778	1			T1	2		T6	1		T104	309
valid_sources[0x3e]	25560	1			T1	1		T103	3		T26	1
valid_sources[0x3f]	26786	1			T1	1		T104	333		T117	1
valid_sources[0x40]	25419	1			T104	337		T117	5		T18	3
valid_sources[0x41]	25247	1			T4	7		T103	1		T104	296
valid_sources[0x42]	26500	1			T1	1		T103	6		T153	1
valid_sources[0x43]	24967	1			T103	1		T104	321		T109	1
valid_sources[0x44]	26052	1			T4	3		T103	2		T104	295
valid_sources[0x45]	26674	1			T1	2		T103	6		T26	2
valid_sources[0x46]	26967	1			T25	1		T6	1		T104	309
valid_sources[0x47]	26409	1			T103	4		T104	327		T119	2
valid_sources[0x48]	25369	1			T1	1		T103	5		T26	1
valid_sources[0x49]	28592	1			T103	3		T104	317		T160	1
valid_sources[0x4a]	27127	1			T103	1		T6	1		T104	331
valid_sources[0x4b]	25419	1			T1	1		T103	2		T153	1
valid_sources[0x4c]	27426	1			T1	1		T4	1		T103	1
valid_sources[0x4d]	29063	1			T4	5		T103	3		T26	4
valid_sources[0x4e]	24792	1			T103	2		T6	1		T104	300
valid_sources[0x4f]	25146	1			T103	1		T104	288		T160	1
valid_sources[0x50]	27335	1			T4	33		T153	1		T6	1
valid_sources[0x51]	24781	1			T103	2		T26	1		T25	1
valid_sources[0x52]	25993	1			T103	5		T26	1		T6	1
valid_sources[0x53]	23099	1			T1	1		T103	1		T104	337
valid_sources[0x54]	25338	1			T7	4		T104	323		T105	1
valid_sources[0x55]	26025	1			T23	1		T103	5		T153	1
valid_sources[0x56]	27025	1			T104	284		T119	1		T115	215
valid_sources[0x57]	24084	1			T4	3		T103	1		T104	321
valid_sources[0x58]	26221	1			T153	1		T104	329		T105	3
valid_sources[0x59]	26640	1			T103	1		T26	1		T104	294
valid_sources[0x5a]	25057	1			T4	10		T103	2		T104	354
valid_sources[0x5b]	23433	1			T103	1		T6	1		T104	323
valid_sources[0x5c]	27729	1			T26	9		T11	1		T104	304
valid_sources[0x5d]	26878	1			T7	2		T103	5		T153	1
valid_sources[0x5e]	24939	1			T4	2		T26	2		T153	1
valid_sources[0x5f]	26465	1			T1	2		T103	3		T104	339
valid_sources[0x60]	25663	1			T103	1		T104	319		T115	197
valid_sources[0x61]	25034	1			T22	1		T6	1		T104	316
valid_sources[0x62]	28238	1			T6	1		T104	268		T18	1
valid_sources[0x63]	24993	1			T1	1		T4	6		T103	4
valid_sources[0x64]	27100	1			T4	23		T6	2		T104	366
valid_sources[0x65]	24616	1			T103	2		T104	333		T160	1
valid_sources[0x66]	25252	1			T4	2		T153	1		T104	324
valid_sources[0x67]	25089	1			T23	3		T103	6		T11	5
valid_sources[0x68]	25306	1			T4	34		T26	1		T104	304
valid_sources[0x69]	25287	1			T1	1		T4	2		T104	314
valid_sources[0x6a]	27118	1			T103	3		T127	1		T11	1
valid_sources[0x6b]	27315	1			T103	3		T104	329		T105	1
valid_sources[0x6c]	24474	1			T1	1		T11	6		T104	345
valid_sources[0x6d]	25378	1			T1	1		T104	312		T105	1
valid_sources[0x6e]	24560	1			T26	1		T14	10		T104	312
valid_sources[0x6f]	28347	1			T104	308		T119	9		T115	216
valid_sources[0x70]	27211	1			T7	1		T103	4		T104	312
valid_sources[0x71]	27120	1			T2	71		T104	339		T115	207
valid_sources[0x72]	24669	1			T1	3		T103	1		T104	322
valid_sources[0x73]	27378	1			T104	290		T105	1		T161	1
valid_sources[0x74]	25727	1			T104	310		T18	2		T109	1
valid_sources[0x75]	26661	1			T4	1		T103	1		T104	325
valid_sources[0x76]	25521	1			T4	6		T153	1		T104	329
valid_sources[0x77]	24989	1			T4	4		T103	2		T104	286
valid_sources[0x78]	25704	1			T103	2		T104	341		T161	1
valid_sources[0x79]	26873	1			T4	5		T103	8		T26	1
valid_sources[0x7a]	25055	1			T1	1		T26	1		T6	1
valid_sources[0x7b]	24857	1			T23	1		T103	7		T6	1
valid_sources[0x7c]	23906	1			T4	24		T103	1		T26	2
valid_sources[0x7d]	25215	1			T103	2		T6	1		T104	328
valid_sources[0x7e]	28487	1			T103	1		T26	1		T6	3
valid_sources[0x7f]	26290	1			T1	1		T7	1		T103	2
valid_sources[0x80]	25479	1			T103	2		T104	326		T161	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1489388

1

T1

2

T2

4

T20

5

values[0x0]

all_enables

biggest_size

2211745

1

T1

31

T2

12

T3

3

values[0x1]

all_enables

biggest_size

2212517

1

T1

34

T2

13

T3

1