Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2580	1			T2	1		T4	2		T7	2
non_zero_bins[1]	1897	1			T2	1		T20	3		T4	4
zero	8446	1			T1	1		T2	5		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	513	1			T29	1		T103	1		T104	6
uni	3555	1			T2	2		T20	2		T4	9
gen	4004	1			T2	2		T3	1		T20	2
res	842	1			T2	1		T20	1		T4	2
ins	4009	1			T1	1		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8800

1

T1

1

T2

5

T3

2

mubi_true

4123

1

T2

2

T20

3

T4

7

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

12923

1

T1

1

T2

7

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	105	1			T103	1		T115	1		T116	3
upd	non_zero_bins[0]	pass	mubi_true	128	1			T104	4		T154	1		T142	1
upd	non_zero_bins[1]	pass	mubi_false	68	1			T29	1		T115	1		T144	3
upd	non_zero_bins[1]	pass	mubi_true	109	1			T104	2		T160	1		T144	3
upd	zero	pass	mubi_false	55	1			T170	1		T196	1		T198	1
upd	zero	pass	mubi_true	48	1			T115	1		T196	2		T242	1
uni	zero	pass	mubi_false	2627	1			T2	2		T20	2		T4	6
uni	zero	pass	mubi_true	928	1			T4	3		T145	1		T146	1
gen	non_zero_bins[0]	pass	mubi_false	559	1			T4	1		T29	1		T103	1
gen	non_zero_bins[0]	pass	mubi_true	496	1			T2	1		T7	1		T103	1
gen	non_zero_bins[1]	pass	mubi_false	372	1			T20	1		T4	1		T7	3
gen	non_zero_bins[1]	pass	mubi_true	302	1			T104	3		T18	1		T118	11
gen	zero	pass	mubi_false	1830	1			T2	1		T3	1		T4	5
gen	zero	pass	mubi_true	445	1			T20	1		T4	1		T29	1
res	non_zero_bins[0]	pass	mubi_false	187	1			T11	2		T104	1		T18	2
res	non_zero_bins[0]	pass	mubi_true	164	1			T103	1		T104	1		T131	1
res	non_zero_bins[1]	pass	mubi_false	160	1			T2	1		T4	1		T7	4
res	non_zero_bins[1]	pass	mubi_true	150	1			T20	1		T4	1		T104	1
res	zero	pass	mubi_false	86	1			T104	2		T147	1		T28	1
res	zero	pass	mubi_true	95	1			T153	1		T104	2		T118	2
ins	non_zero_bins[0]	pass	mubi_false	489	1			T7	1		T145	1		T104	8
ins	non_zero_bins[0]	pass	mubi_true	452	1			T4	1		T103	1		T145	1
ins	non_zero_bins[1]	pass	mubi_false	399	1			T4	1		T11	1		T104	4
ins	non_zero_bins[1]	pass	mubi_true	337	1			T20	1		T103	1		T104	8
ins	zero	pass	mubi_false	1863	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	469	1			T2	1		T4	1		T7	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded