Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T24

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T20
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T92,T93,T94
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T20
DataWait->AckPls	80	Covered	T2,T3,T20
DataWait->Disabled	107	Covered	T24,T74,T155
DataWait->Error	99	Covered	T1,T5,T27
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T4,T142,T175
EndPointClear->Error	99	Covered	T176,T66,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T1,T4,T7
Idle->Error	99	Covered	T1,T3,T14

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T20
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T20
DataWait	-	-	-	0	Covered	T1,T2,T20
AckPls	-	-	-	-	Covered	T2,T3,T20
Error	-	-	-	-	Covered	T1,T3,T14
default	-	-	-	-	Covered	T1,T14,T71

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T14
0	1	Covered	T1,T7,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1732486763	974100	0	0
FpvSecCmErrorStEscalate_A	1732486763	981359	0	0
u_state_regs_A	1732455335	1731282723	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1732486763	974100	0	0
T1	11718	4311	0	0
T2	20272	0	0	0
T3	6888	2639	0	0
T4	165865	0	0	0
T5	0	7770	0	0
T6	0	2464	0	0
T7	15855	0	0	0
T12	0	7798	0	0
T13	0	7924	0	0
T14	0	2400	0	0
T20	39235	0	0	0
T21	7049	0	0	0
T22	13391	0	0	0
T23	18193	0	0	0
T24	4760	0	0	0
T27	0	7770	0	0
T71	0	7517	0	0
T105	0	7770	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1732486763	981359	0	0
T1	11718	4318	0	0
T2	20272	0	0	0
T3	6888	2646	0	0
T4	165865	0	0	0
T5	0	7777	0	0
T6	0	2471	0	0
T7	15855	0	0	0
T12	0	7805	0	0
T13	0	7931	0	0
T14	0	2407	0	0
T20	39235	0	0	0
T21	7049	0	0	0
T22	13391	0	0	0
T23	18193	0	0	0
T24	4760	0	0	0
T27	0	7777	0	0
T71	0	7524	0	0
T105	0	7777	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1732455335	1731282723	0	0
T1	11462	10258	0	0
T2	20272	19719	0	0
T3	6747	5725	0	0
T4	165865	159040	0	0
T7	15855	15316	0	0
T20	39235	38675	0	0
T21	7049	6391	0	0
T22	13391	12768	0	0
T23	18193	17752	0	0
T24	4760	4088	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T117,T118
DataWait	75	Covered	T20,T117,T118
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T117,T118
DataWait->AckPls	80	Covered	T20,T117,T118
DataWait->Disabled	107	Covered	T177,T178
DataWait->Error	99	Covered	T99,T100,T179
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T4,T142,T175
EndPointClear->Error	99	Covered	T176,T66,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T117,T118
Idle->Disabled	107	Covered	T1,T4,T7
Idle->Error	99	Covered	T1,T3,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T117,T118
Idle	-	1	0	-	Covered	T20,T117,T118
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T117,T118
DataWait	-	-	-	0	Covered	T20,T117,T118
AckPls	-	-	-	-	Covered	T20,T117,T118
Error	-	-	-	-	Covered	T1,T3,T14
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T14
0	1	Covered	T1,T7,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	247498109	139500	0	0
FpvSecCmErrorStEscalate_A	247498109	140537	0	0
u_state_regs_A	247498109	247330593	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	139500	0	0
T1	1674	623	0	0
T2	2896	0	0	0
T3	984	377	0	0
T4	23695	0	0	0
T5	0	1110	0	0
T6	0	352	0	0
T7	2265	0	0	0
T12	0	1114	0	0
T13	0	1132	0	0
T14	0	350	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1110	0	0
T71	0	1081	0	0
T105	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	140537	0	0
T1	1674	624	0	0
T2	2896	0	0	0
T3	984	378	0	0
T4	23695	0	0	0
T5	0	1111	0	0
T6	0	353	0	0
T7	2265	0	0	0
T12	0	1115	0	0
T13	0	1133	0	0
T14	0	351	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1111	0	0
T71	0	1082	0	0
T105	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T7,T26
DataWait	75	Covered	T20,T7,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T7,T26
DataWait->AckPls	80	Covered	T20,T7,T26
DataWait->Disabled	107	Covered	T155,T54,T180
DataWait->Error	99	Covered	T36,T181,T182
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T4,T142,T175
EndPointClear->Error	99	Covered	T176,T66,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T7,T26
Idle->Disabled	107	Covered	T1,T4,T7
Idle->Error	99	Covered	T1,T3,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T7,T26
Idle	-	1	0	-	Covered	T20,T7,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T7,T26
DataWait	-	-	-	0	Covered	T20,T7,T153
AckPls	-	-	-	-	Covered	T20,T7,T26
Error	-	-	-	-	Covered	T1,T3,T14
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T14
0	1	Covered	T1,T7,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	247498109	139500	0	0
FpvSecCmErrorStEscalate_A	247498109	140537	0	0
u_state_regs_A	247498109	247330593	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	139500	0	0
T1	1674	623	0	0
T2	2896	0	0	0
T3	984	377	0	0
T4	23695	0	0	0
T5	0	1110	0	0
T6	0	352	0	0
T7	2265	0	0	0
T12	0	1114	0	0
T13	0	1132	0	0
T14	0	350	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1110	0	0
T71	0	1081	0	0
T105	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	140537	0	0
T1	1674	624	0	0
T2	2896	0	0	0
T3	984	378	0	0
T4	23695	0	0	0
T5	0	1111	0	0
T6	0	353	0	0
T7	2265	0	0	0
T12	0	1115	0	0
T13	0	1133	0	0
T14	0	351	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1111	0	0
T71	0	1082	0	0
T105	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T24,T26
DataWait	75	Covered	T20,T24,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T24,T26
DataWait->AckPls	80	Covered	T20,T24,T26
DataWait->Disabled	107	Covered	T24,T183,T184
DataWait->Error	99	Covered	T14,T105,T79
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T4,T142,T175
EndPointClear->Error	99	Covered	T176,T66,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T24,T26
Idle->Disabled	107	Covered	T1,T4,T7
Idle->Error	99	Covered	T1,T3,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T24,T26
Idle	-	1	0	-	Covered	T20,T24,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T24,T26
DataWait	-	-	-	0	Covered	T20,T24,T26
AckPls	-	-	-	-	Covered	T20,T24,T26
Error	-	-	-	-	Covered	T1,T3,T14
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T14
0	1	Covered	T1,T7,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	247498109	139500	0	0
FpvSecCmErrorStEscalate_A	247498109	140537	0	0
u_state_regs_A	247498109	247330593	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	139500	0	0
T1	1674	623	0	0
T2	2896	0	0	0
T3	984	377	0	0
T4	23695	0	0	0
T5	0	1110	0	0
T6	0	352	0	0
T7	2265	0	0	0
T12	0	1114	0	0
T13	0	1132	0	0
T14	0	350	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1110	0	0
T71	0	1081	0	0
T105	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	140537	0	0
T1	1674	624	0	0
T2	2896	0	0	0
T3	984	378	0	0
T4	23695	0	0	0
T5	0	1111	0	0
T6	0	353	0	0
T7	2265	0	0	0
T12	0	1115	0	0
T13	0	1133	0	0
T14	0	351	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1111	0	0
T71	0	1082	0	0
T105	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T8,T117,T118
DataWait	75	Covered	T8,T117,T118
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T8,T117,T118
DataWait->AckPls	80	Covered	T8,T117,T118
DataWait->Disabled	107	Covered	T67,T68,T185
DataWait->Error	99	Covered	T186,T187
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T4,T142,T175
EndPointClear->Error	99	Covered	T176,T66,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T8,T117,T118
Idle->Disabled	107	Covered	T1,T4,T7
Idle->Error	99	Covered	T1,T3,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T117,T118
Idle	-	1	0	-	Covered	T8,T117,T118
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T117,T118
DataWait	-	-	-	0	Covered	T8,T117,T118
AckPls	-	-	-	-	Covered	T8,T117,T118
Error	-	-	-	-	Covered	T1,T3,T14
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T14
0	1	Covered	T1,T7,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	247498109	139500	0	0
FpvSecCmErrorStEscalate_A	247498109	140537	0	0
u_state_regs_A	247498109	247330593	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	139500	0	0
T1	1674	623	0	0
T2	2896	0	0	0
T3	984	377	0	0
T4	23695	0	0	0
T5	0	1110	0	0
T6	0	352	0	0
T7	2265	0	0	0
T12	0	1114	0	0
T13	0	1132	0	0
T14	0	350	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1110	0	0
T71	0	1081	0	0
T105	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	140537	0	0
T1	1674	624	0	0
T2	2896	0	0	0
T3	984	378	0	0
T4	23695	0	0	0
T5	0	1111	0	0
T6	0	353	0	0
T7	2265	0	0	0
T12	0	1115	0	0
T13	0	1133	0	0
T14	0	351	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1111	0	0
T71	0	1082	0	0
T105	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T20
DataWait	75	Covered	T2,T3,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T92
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T20
DataWait->AckPls	80	Covered	T2,T3,T20
DataWait->Disabled	107	Covered	T188,T37,T39
DataWait->Error	99	Covered	T27,T169,T43
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T4,T142,T175
EndPointClear->Error	99	Covered	T176,T66,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T20
Idle->Disabled	107	Covered	T1,T4,T7
Idle->Error	99	Covered	T3,T12,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T20
Idle	-	1	0	-	Covered	T2,T3,T20
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T20
DataWait	-	-	-	0	Covered	T2,T20,T4
AckPls	-	-	-	-	Covered	T2,T3,T20
Error	-	-	-	-	Covered	T1,T3,T14
default	-	-	-	-	Covered	T1,T14,T71

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T14
0	1	Covered	T1,T7,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	247498109	137100	0	0
FpvSecCmErrorStEscalate_A	247498109	138137	0	0
u_state_regs_A	247466681	247299165	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	137100	0	0
T1	1674	573	0	0
T2	2896	0	0	0
T3	984	377	0	0
T4	23695	0	0	0
T5	0	1110	0	0
T6	0	352	0	0
T7	2265	0	0	0
T12	0	1114	0	0
T13	0	1132	0	0
T14	0	300	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1110	0	0
T71	0	1031	0	0
T105	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	138137	0	0
T1	1674	574	0	0
T2	2896	0	0	0
T3	984	378	0	0
T4	23695	0	0	0
T5	0	1111	0	0
T6	0	353	0	0
T7	2265	0	0	0
T12	0	1115	0	0
T13	0	1133	0	0
T14	0	301	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1111	0	0
T71	0	1032	0	0
T105	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247466681	247299165	0	0
T1	1418	1246	0	0
T2	2896	2817	0	0
T3	843	697	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T7,T8
DataWait	75	Covered	T1,T20,T7
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T93
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T7,T8
DataWait->AckPls	80	Covered	T20,T7,T8
DataWait->Disabled	107	Covered	T38,T189,T190
DataWait->Error	99	Covered	T1,T5,T191
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T4,T142,T175
EndPointClear->Error	99	Covered	T176,T66,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T20,T7
Idle->Disabled	107	Covered	T1,T4,T7
Idle->Error	99	Covered	T3,T14,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T7,T8
Idle	-	1	0	-	Covered	T1,T20,T7
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T7,T8
DataWait	-	-	-	0	Covered	T1,T20,T7
AckPls	-	-	-	-	Covered	T20,T7,T8
Error	-	-	-	-	Covered	T1,T3,T14
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T14
0	1	Covered	T1,T7,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	247498109	139500	0	0
FpvSecCmErrorStEscalate_A	247498109	140537	0	0
u_state_regs_A	247498109	247330593	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	139500	0	0
T1	1674	623	0	0
T2	2896	0	0	0
T3	984	377	0	0
T4	23695	0	0	0
T5	0	1110	0	0
T6	0	352	0	0
T7	2265	0	0	0
T12	0	1114	0	0
T13	0	1132	0	0
T14	0	350	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1110	0	0
T71	0	1081	0	0
T105	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	140537	0	0
T1	1674	624	0	0
T2	2896	0	0	0
T3	984	378	0	0
T4	23695	0	0	0
T5	0	1111	0	0
T6	0	353	0	0
T7	2265	0	0	0
T12	0	1115	0	0
T13	0	1133	0	0
T14	0	351	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1111	0	0
T71	0	1082	0	0
T105	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T25,T8
DataWait	75	Covered	T20,T25,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T94
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T25,T8
DataWait->AckPls	80	Covered	T20,T25,T8
DataWait->Disabled	107	Covered	T74,T80,T55
DataWait->Error	99	Covered	T192,T88
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T4,T142,T175
EndPointClear->Error	99	Covered	T176,T66,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T25,T8
Idle->Disabled	107	Covered	T1,T4,T7
Idle->Error	99	Covered	T1,T3,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T25,T8
Idle	-	1	0	-	Covered	T20,T25,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T25,T8
DataWait	-	-	-	0	Covered	T20,T25,T8
AckPls	-	-	-	-	Covered	T20,T25,T8
Error	-	-	-	-	Covered	T1,T3,T14
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T14
0	1	Covered	T1,T7,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	247498109	139500	0	0
FpvSecCmErrorStEscalate_A	247498109	140537	0	0
u_state_regs_A	247498109	247330593	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	139500	0	0
T1	1674	623	0	0
T2	2896	0	0	0
T3	984	377	0	0
T4	23695	0	0	0
T5	0	1110	0	0
T6	0	352	0	0
T7	2265	0	0	0
T12	0	1114	0	0
T13	0	1132	0	0
T14	0	350	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1110	0	0
T71	0	1081	0	0
T105	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	140537	0	0
T1	1674	624	0	0
T2	2896	0	0	0
T3	984	378	0	0
T4	23695	0	0	0
T5	0	1111	0	0
T6	0	353	0	0
T7	2265	0	0	0
T12	0	1115	0	0
T13	0	1133	0	0
T14	0	351	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1111	0	0
T71	0	1082	0	0
T105	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0