Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T111,T110,T112
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T109,T108,T113
1	0	1	Covered	T1,T7,T14
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T5

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	494309172	587309	0	0
DepthKnown_A	494996218	494661186	0	0
RvalidKnown_A	494996218	494661186	0	0
WreadyKnown_A	494996218	494661186	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	494653984	662792	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494309172	587309	0	0
T1	704	254	0	0
T2	5792	0	0	0
T3	718	0	0	0
T4	47390	0	0	0
T5	0	55	0	0
T6	0	85	0	0
T7	4530	2060	0	0
T8	0	2055	0	0
T11	0	953	0	0
T18	0	5597	0	0
T20	11210	0	0	0
T21	2014	0	0	0
T22	3826	0	0	0
T23	5198	0	0	0
T24	1360	0	0	0
T28	0	831	0	0
T105	0	79	0	0
T118	0	2739	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494996218	494661186	0	0
T1	3348	3004	0	0
T2	5792	5634	0	0
T3	1968	1676	0	0
T4	47390	45440	0	0
T7	4530	4376	0	0
T20	11210	11050	0	0
T21	2014	1826	0	0
T22	3826	3648	0	0
T23	5198	5072	0	0
T24	1360	1168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494996218	494661186	0	0
T1	3348	3004	0	0
T2	5792	5634	0	0
T3	1968	1676	0	0
T4	47390	45440	0	0
T7	4530	4376	0	0
T20	11210	11050	0	0
T21	2014	1826	0	0
T22	3826	3648	0	0
T23	5198	5072	0	0
T24	1360	1168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494996218	494661186	0	0
T1	3348	3004	0	0
T2	5792	5634	0	0
T3	1968	1676	0	0
T4	47390	45440	0	0
T7	4530	4376	0	0
T20	11210	11050	0	0
T21	2014	1826	0	0
T22	3826	3648	0	0
T23	5198	5072	0	0
T24	1360	1168	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	494653984	662792	0	0
T1	3348	1426	0	0
T2	5792	0	0	0
T3	1968	0	0	0
T4	47390	0	0	0
T5	0	1534	0	0
T6	0	755	0	0
T7	4530	2060	0	0
T8	0	2055	0	0
T11	0	953	0	0
T12	0	293	0	0
T14	0	312	0	0
T20	11210	0	0	0
T21	2014	0	0	0
T22	3826	0	0	0
T23	5198	0	0	0
T24	1360	0	0	0
T71	0	222	0	0
T105	0	3352	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T162,T34,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T111,T163,T164
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T108,T113,T165
1	0	1	Covered	T1,T7,T14
1	1	0	Not Covered
1	1	1	Covered	T7,T11,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	247154586	288809	0	0
DepthKnown_A	247498109	247330593	0	0
RvalidKnown_A	247498109	247330593	0	0
WreadyKnown_A	247498109	247330593	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	247326992	326668	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247154586	288809	0	0
T1	352	124	0	0
T2	2896	0	0	0
T3	359	0	0	0
T4	23695	0	0	0
T5	0	15	0	0
T6	0	33	0	0
T7	2265	1025	0	0
T8	0	1026	0	0
T11	0	424	0	0
T18	0	2766	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T28	0	400	0	0
T105	0	35	0	0
T118	0	1356	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	247326992	326668	0	0
T1	1674	716	0	0
T2	2896	0	0	0
T3	984	0	0	0
T4	23695	0	0	0
T5	0	798	0	0
T6	0	367	0	0
T7	2265	1025	0	0
T8	0	1026	0	0
T11	0	424	0	0
T12	0	150	0	0
T14	0	157	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T71	0	112	0	0
T105	0	1663	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T110,T112,T166
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T109,T167
1	0	1	Covered	T1,T7,T14
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	247154586	298500	0	0
DepthKnown_A	247498109	247330593	0	0
RvalidKnown_A	247498109	247330593	0	0
WreadyKnown_A	247498109	247330593	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	247326992	336124	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247154586	298500	0	0
T1	352	130	0	0
T2	2896	0	0	0
T3	359	0	0	0
T4	23695	0	0	0
T5	0	40	0	0
T6	0	52	0	0
T7	2265	1035	0	0
T8	0	1029	0	0
T11	0	529	0	0
T18	0	2831	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T28	0	431	0	0
T105	0	44	0	0
T118	0	1383	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	247326992	336124	0	0
T1	1674	710	0	0
T2	2896	0	0	0
T3	984	0	0	0
T4	23695	0	0	0
T5	0	736	0	0
T6	0	388	0	0
T7	2265	1035	0	0
T8	0	1029	0	0
T11	0	529	0	0
T12	0	143	0	0
T14	0	155	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T71	0	110	0	0
T105	0	1689	0	0