Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	137	1			T21	1		T26	1		T27	1
auto_req_mode	139	1			T2	1		T3	1		T8	1
sw_mode	2689	1			T17	1		T18	1		T102	17

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

290

1

T2

1

T3

1

T17

1

single

110

1

T8

1

T18

1

T21

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1311	1			T8	1		T106	1		T21	1
auto[2]	110	1			T127	1		T268	1		T269	1
auto[3]	90	1			T17	1		T19	1		T130	1
auto[4]	17	1			T118	1		T28	1		T239	1
auto[5]	68	1			T133	1		T135	1		T270	1
auto[6]	233	1			T137	1		T271	1		T272	27
auto[7]	1136	1			T2	1		T3	1		T18	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	89	1			T21	1		T27	1		T91	1
auto[1]	auto_req_mode	83	1			T8	1		T126	1		T31	1
auto[1]	sw_mode	1139	1			T106	1		T103	8		T116	68
auto[2]	boot_req_mode	3	1			T269	1		T273	1		T274	1
auto[2]	auto_req_mode	3	1			T275	1		T276	1		T277	1
auto[2]	sw_mode	104	1			T127	1		T268	1		T192	41
auto[3]	boot_req_mode	3	1			T278	1		T279	1		T280	1
auto[3]	auto_req_mode	3	1			T19	1		T130	1		T281	1
auto[3]	sw_mode	84	1			T17	1		T282	1		T283	1
auto[4]	boot_req_mode	8	1			T28	1		T239	1		T284	1
auto[4]	auto_req_mode	3	1			T118	1		T285	1		T286	1
auto[4]	sw_mode	6	1			T287	1		T288	1		T289	4
auto[5]	boot_req_mode	4	1			T135	1		T270	1		T290	1
auto[5]	auto_req_mode	4	1			T133	1		T291	1		T292	1
auto[5]	sw_mode	60	1			T293	1		T294	1		T295	1
auto[6]	boot_req_mode	6	1			T271	1		T296	1		T297	1
auto[6]	auto_req_mode	5	1			T298	1		T299	1		T300	1
auto[6]	sw_mode	222	1			T137	1		T272	27		T204	5
auto[7]	boot_req_mode	24	1			T26	1		T134	1		T301	1
auto[7]	auto_req_mode	38	1			T2	1		T3	1		T15	1
auto[7]	sw_mode	1074	1			T18	1		T102	17		T119	1