Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	593183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4615751

1

T1

6

T2

63

T3

43

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1390467	1			T1	16		T2	305		T3	49
values[0x0]	1766472	1			T1	6		T2	31		T3	22
values[0x1]	2051995	1			T1	4		T2	33		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	297997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4910937

1

T1

12

T2

163

T3

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20567	1			T2	2		T8	2		T4	2
valid_sources[0x01]	20235	1			T2	4		T4	5		T19	2
valid_sources[0x02]	20304	1			T4	1		T102	323		T116	531
valid_sources[0x03]	21047	1			T2	3		T19	1		T102	337
valid_sources[0x04]	20378	1			T2	1		T4	6		T18	2
valid_sources[0x05]	19518	1			T102	347		T116	472		T119	2
valid_sources[0x06]	20682	1			T2	3		T4	2		T19	2
valid_sources[0x07]	20619	1			T2	1		T4	3		T18	1
valid_sources[0x08]	20230	1			T8	4		T4	2		T102	273
valid_sources[0x09]	20170	1			T2	2		T8	1		T4	5
valid_sources[0x0a]	19650	1			T2	2		T8	4		T18	1
valid_sources[0x0b]	20281	1			T8	1		T4	2		T102	322
valid_sources[0x0c]	19678	1			T2	4		T102	327		T116	469
valid_sources[0x0d]	19422	1			T4	3		T18	2		T19	3
valid_sources[0x0e]	20506	1			T4	4		T102	310		T116	535
valid_sources[0x0f]	19938	1			T2	1		T4	2		T19	1
valid_sources[0x10]	20840	1			T4	1		T102	331		T116	474
valid_sources[0x11]	20460	1			T2	4		T4	2		T102	361
valid_sources[0x12]	18964	1			T18	2		T102	308		T106	1
valid_sources[0x13]	20927	1			T2	1		T4	2		T102	327
valid_sources[0x14]	20567	1			T2	2		T4	1		T19	3
valid_sources[0x15]	20482	1			T2	2		T4	3		T102	300
valid_sources[0x16]	20026	1			T2	3		T8	1		T4	5
valid_sources[0x17]	19871	1			T2	2		T4	4		T19	2
valid_sources[0x18]	21145	1			T19	1		T102	328		T116	503
valid_sources[0x19]	19823	1			T4	3		T102	306		T116	486
valid_sources[0x1a]	23137	1			T2	1		T4	4		T102	327
valid_sources[0x1b]	20595	1			T2	1		T8	1		T4	5
valid_sources[0x1c]	19879	1			T2	1		T4	2		T18	4
valid_sources[0x1d]	19773	1			T2	2		T4	2		T19	2
valid_sources[0x1e]	21259	1			T2	2		T4	3		T18	2
valid_sources[0x1f]	20185	1			T2	2		T4	3		T102	308
valid_sources[0x20]	21119	1			T2	2		T4	4		T19	1
valid_sources[0x21]	21360	1			T2	3		T4	5		T102	303
valid_sources[0x22]	20054	1			T4	6		T102	348		T116	511
valid_sources[0x23]	19347	1			T2	2		T4	7		T19	2
valid_sources[0x24]	19738	1			T8	4		T4	5		T102	298
valid_sources[0x25]	20068	1			T8	3		T4	1		T102	324
valid_sources[0x26]	20360	1			T19	5		T102	316		T116	433
valid_sources[0x27]	19674	1			T2	4		T4	2		T102	337
valid_sources[0x28]	19458	1			T4	3		T19	1		T102	325
valid_sources[0x29]	20369	1			T2	1		T102	334		T116	385
valid_sources[0x2a]	20903	1			T2	2		T4	2		T19	1
valid_sources[0x2b]	19918	1			T2	3		T4	6		T19	1
valid_sources[0x2c]	19333	1			T4	3		T102	316		T116	475
valid_sources[0x2d]	20429	1			T2	1		T4	3		T18	3
valid_sources[0x2e]	20265	1			T2	3		T4	1		T102	322
valid_sources[0x2f]	20331	1			T2	2		T4	1		T18	1
valid_sources[0x30]	19890	1			T2	2		T8	1		T4	2
valid_sources[0x31]	22055	1			T2	1		T4	1		T19	1
valid_sources[0x32]	19541	1			T2	2		T4	2		T19	1
valid_sources[0x33]	20673	1			T2	6		T4	2		T19	1
valid_sources[0x34]	21141	1			T2	1		T8	1		T18	2
valid_sources[0x35]	20736	1			T2	1		T4	3		T102	304
valid_sources[0x36]	20609	1			T2	1		T8	3		T4	5
valid_sources[0x37]	19833	1			T4	2		T19	2		T102	290
valid_sources[0x38]	19834	1			T2	2		T19	1		T102	317
valid_sources[0x39]	20634	1			T2	1		T4	4		T18	3
valid_sources[0x3a]	19783	1			T2	2		T18	3		T102	315
valid_sources[0x3b]	20374	1			T4	4		T102	308		T116	471
valid_sources[0x3c]	20026	1			T2	1		T8	3		T4	5
valid_sources[0x3d]	19515	1			T2	2		T102	316		T116	486
valid_sources[0x3e]	19799	1			T4	1		T19	1		T102	284
valid_sources[0x3f]	20530	1			T2	1		T8	1		T4	2
valid_sources[0x40]	20232	1			T2	1		T4	1		T102	291
valid_sources[0x41]	19740	1			T2	3		T4	1		T102	299
valid_sources[0x42]	20338	1			T2	2		T18	1		T19	6
valid_sources[0x43]	18914	1			T2	1		T4	2		T18	2
valid_sources[0x44]	20488	1			T2	2		T4	1		T19	1
valid_sources[0x45]	21852	1			T2	2		T4	1		T102	315
valid_sources[0x46]	21552	1			T2	1		T8	2		T4	3
valid_sources[0x47]	19938	1			T2	2		T4	1		T19	3
valid_sources[0x48]	20078	1			T2	1		T8	5		T4	1
valid_sources[0x49]	20745	1			T2	4		T4	4		T19	4
valid_sources[0x4a]	20741	1			T4	2		T102	321		T106	2
valid_sources[0x4b]	19459	1			T2	1		T4	7		T19	5
valid_sources[0x4c]	20767	1			T2	4		T4	3		T102	290
valid_sources[0x4d]	20833	1			T2	1		T4	4		T19	2
valid_sources[0x4e]	21468	1			T2	1		T8	4		T19	1
valid_sources[0x4f]	19813	1			T2	1		T4	1		T18	4
valid_sources[0x50]	19540	1			T2	3		T4	2		T19	1
valid_sources[0x51]	19865	1			T4	1		T18	7		T102	332
valid_sources[0x52]	20727	1			T2	1		T4	2		T19	3
valid_sources[0x53]	19859	1			T2	3		T4	1		T102	332
valid_sources[0x54]	20263	1			T2	2		T19	2		T102	310
valid_sources[0x55]	18861	1			T4	2		T102	314		T116	518
valid_sources[0x56]	22092	1			T8	6		T4	1		T19	4
valid_sources[0x57]	20661	1			T2	4		T4	2		T102	346
valid_sources[0x58]	19812	1			T8	2		T19	1		T102	312
valid_sources[0x59]	19876	1			T2	1		T102	314		T116	487
valid_sources[0x5a]	19676	1			T2	2		T4	5		T102	304
valid_sources[0x5b]	21672	1			T2	1		T4	1		T18	5
valid_sources[0x5c]	19755	1			T2	6		T4	3		T18	1
valid_sources[0x5d]	20707	1			T2	1		T4	1		T19	5
valid_sources[0x5e]	20711	1			T2	1		T4	1		T102	298
valid_sources[0x5f]	20974	1			T4	4		T19	1		T102	349
valid_sources[0x60]	20749	1			T2	6		T4	2		T19	3
valid_sources[0x61]	19090	1			T2	1		T4	1		T19	1
valid_sources[0x62]	20126	1			T4	1		T18	2		T102	347
valid_sources[0x63]	20698	1			T2	1		T4	6		T18	5
valid_sources[0x64]	19816	1			T2	2		T4	10		T102	305
valid_sources[0x65]	19950	1			T4	6		T102	343		T116	537
valid_sources[0x66]	18869	1			T2	2		T4	2		T19	5
valid_sources[0x67]	20318	1			T2	1		T8	6		T4	2
valid_sources[0x68]	21085	1			T4	6		T102	305		T116	505
valid_sources[0x69]	19232	1			T2	1		T4	2		T102	313
valid_sources[0x6a]	20904	1			T19	3		T102	308		T106	2
valid_sources[0x6b]	20149	1			T2	3		T4	5		T102	318
valid_sources[0x6c]	19185	1			T2	1		T4	2		T18	3
valid_sources[0x6d]	20653	1			T2	2		T4	2		T19	2
valid_sources[0x6e]	21037	1			T1	26		T2	1		T4	3
valid_sources[0x6f]	20432	1			T2	1		T4	2		T19	1
valid_sources[0x70]	19720	1			T2	1		T4	2		T102	326
valid_sources[0x71]	19758	1			T2	2		T4	3		T18	5
valid_sources[0x72]	20780	1			T4	1		T19	1		T102	332
valid_sources[0x73]	20251	1			T2	1		T4	2		T102	300
valid_sources[0x74]	19330	1			T2	1		T102	308		T116	519
valid_sources[0x75]	19692	1			T4	1		T19	1		T102	327
valid_sources[0x76]	21095	1			T2	2		T8	1		T4	3
valid_sources[0x77]	20231	1			T102	310		T116	442		T25	2
valid_sources[0x78]	21058	1			T4	4		T102	319		T116	465
valid_sources[0x79]	19553	1			T2	2		T4	2		T102	328
valid_sources[0x7a]	18869	1			T2	1		T102	359		T116	479
valid_sources[0x7b]	20235	1			T2	2		T102	288		T116	439
valid_sources[0x7c]	20298	1			T4	3		T102	299		T106	1
valid_sources[0x7d]	20236	1			T2	1		T4	2		T18	3
valid_sources[0x7e]	20080	1			T4	4		T102	343		T116	517
valid_sources[0x7f]	20895	1			T2	2		T8	1		T4	2
valid_sources[0x80]	21044	1			T2	1		T4	1		T102	305

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1162618

1

T1

1

T2

2

T3

5

values[0x0]

all_enables

biggest_size

1728455

1

T1

3

T2

30

T3

20

values[0x1]

all_enables

biggest_size

1724678

1

T1

2

T2

31

T3

18