Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2496	1			T2	6		T3	3		T8	1
non_zero_bins[1]	1787	1			T2	1		T3	1		T8	3
zero	8158	1			T1	2		T2	1		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	524	1			T102	2		T103	1		T116	8
uni	3435	1			T2	1		T3	1		T17	2
gen	3780	1			T1	1		T2	4		T3	4
res	804	1			T2	2		T3	2		T8	3
ins	3898	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8381

1

T1

2

T2

7

T3

4

mubi_true

4060

1

T2

1

T3

4

T8

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

12441

1

T1

2

T2

8

T3

8

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	130	1			T102	2		T103	1		T116	2
upd	non_zero_bins[0]	pass	mubi_true	127	1			T116	2		T124	2		T125	2
upd	non_zero_bins[1]	pass	mubi_false	89	1			T116	1		T117	1		T188	2
upd	non_zero_bins[1]	pass	mubi_true	92	1			T116	2		T117	3		T189	5
upd	zero	pass	mubi_false	42	1			T117	3		T189	2		T192	1
upd	zero	pass	mubi_true	44	1			T116	1		T117	1		T188	1
uni	zero	pass	mubi_false	2522	1			T2	1		T3	1		T17	2
uni	zero	pass	mubi_true	913	1			T18	1		T102	5		T106	1
gen	non_zero_bins[0]	pass	mubi_false	459	1			T2	3		T18	1		T102	1
gen	non_zero_bins[0]	pass	mubi_true	422	1			T3	3		T19	3		T102	2
gen	non_zero_bins[1]	pass	mubi_false	336	1			T2	1		T17	1		T102	4
gen	non_zero_bins[1]	pass	mubi_true	358	1			T19	1		T102	3		T15	3
gen	zero	pass	mubi_false	1770	1			T1	1		T3	1		T102	4
gen	zero	pass	mubi_true	435	1			T8	3		T102	3		T21	1
res	non_zero_bins[0]	pass	mubi_false	167	1			T2	2		T102	1		T15	2
res	non_zero_bins[0]	pass	mubi_true	182	1			T102	1		T116	5		T117	2
res	non_zero_bins[1]	pass	mubi_false	135	1			T8	3		T116	1		T119	1
res	non_zero_bins[1]	pass	mubi_true	136	1			T16	2		T116	1		T128	1
res	zero	pass	mubi_false	85	1			T3	2		T19	2		T116	1
res	zero	pass	mubi_true	99	1			T102	1		T116	2		T117	1
ins	non_zero_bins[0]	pass	mubi_false	505	1			T8	1		T19	1		T102	4
ins	non_zero_bins[0]	pass	mubi_true	504	1			T2	1		T17	1		T102	6
ins	non_zero_bins[1]	pass	mubi_false	314	1			T17	1		T102	3		T103	1
ins	non_zero_bins[1]	pass	mubi_true	327	1			T3	1		T102	2		T103	1
ins	zero	pass	mubi_false	1827	1			T1	1		T8	1		T5	1
ins	zero	pass	mubi_true	421	1			T18	1		T102	4		T103	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded