Group : csrng_agent_pkg::device_genbits_cg
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Group : csrng_agent_pkg::device_genbits_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
64.29 64.29 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_genbits_cg 64.29 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_genbits_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
64.29 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33
Crosses 8 4 4 50.00


Variables for Group Instance csrng_agent_pkg.csrng_device_genbits_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_glen 4 0 4 100.00 100 1 1 0
csrng_sts 2 1 1 50.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_genbits_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_genbits_cross 8 4 4 50.00 100 1 1 0


Summary for Variable csrng_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for csrng_glen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
glens[0] 2130 1 T1 1 T3 3 T8 3
glens[1] 43 1 T15 1 T133 1 T239 1
glens[2] 40 1 T3 1 T240 1 T129 1
glens[3] 36 1 T19 1 T26 1 T241 1



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for csrng_sts

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
fail 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
pass 3780 1 T1 1 T2 4 T3 4



Summary for Cross csrng_genbits_cross

Samples crossed: csrng_glen csrng_sts
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 4 4 50.00 4


Automatically Generated Cross Bins for csrng_genbits_cross

Element holes
csrng_glencsrng_stsCOUNTAT LEASTNUMBERSTATUS
* [fail] -- -- 4


Covered bins
csrng_glencsrng_stsCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
glens[0] pass 2130 1 T1 1 T3 3 T8 3
glens[1] pass 43 1 T15 1 T133 1 T239 1
glens[2] pass 40 1 T3 1 T240 1 T129 1
glens[3] pass 36 1 T19 1 T26 1 T241 1

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