Unified Coverage Report :: Group :: csrng_agent_pkg::device_genbits_cg

Group : csrng_agent_pkg::device_genbits_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
64.29	64.29	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_genbits_cg	64.29	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_genbits_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
64.29	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33
Crosses	8	4	4	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_glen	4	0	4	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_genbits_cross	8	4	4	50.00	100	1	1	0

Summary for Variable csrng_glen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_glen

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
glens[0]	2130	1			T1	1		T3	3		T8	3
glens[1]	43	1			T15	1		T133	1		T239	1
glens[2]	40	1			T3	1		T240	1		T129	1
glens[3]	36	1			T19	1		T26	1		T241	1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

3780

1

T1

1

T2

4

T3

4

---

Summary for Cross csrng_genbits_cross

Samples crossed: csrng_glen csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	4	4	50.00	4

Automatically Generated Cross Bins for csrng_genbits_cross

Element holes

csrng_glen	csrng_sts	COUNT	AT LEAST	NUMBER	STATUS
*	[fail]	--	--	4

Covered bins

csrng_glen

csrng_sts

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

glens[0]

pass

2130

1

T1

1

T3

3

T8

3

glens[1]

pass

43

1

T15

1

T133

1

T239

1

glens[2]

pass

40

1

T3

1

T240

1

T129

1

glens[3]

pass

36

1

T19

1

T26

1

T241

1