Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.36	100.00	94.44		79.73	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	94.36	100.00	94.44		79.73	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.36	100.00	94.44		79.73	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.38	100.00	94.44		79.73	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		106	106	100.00
ALWAYS	41	3	3	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	46	102	102	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	3	3
43	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
76	1	1
77	1	1
80	1	1
81	1	1
			MISSING_ELSE
85	1	1
86	1	1
89	1	1
90	1	1
			MISSING_ELSE
94	1	1
97	1	1
98	1	1
			MISSING_ELSE
102	1	1
103	1	1
106	1	1
107	1	1
108	1	1
			MISSING_ELSE
113	1	1
114	1	1
115	1	1
			MISSING_ELSE
119	1	1
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
127	1	1
			MISSING_ELSE
131	1	1
132	1	1
133	1	1
134	1	1
136	1	1
137	1	1
139	1	1
144	1	1
145	1	1
146	1	1
149	1	1
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
156	1	1
157	1	1
158	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
168	1	1
171	1	1
174	1	1
182	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T24,T22

 LINE       64
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T5,T25
1	1	Covered	T2,T3,T8

 LINE       182
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T25,T24
1	0	Covered	T1,T4,T5

 LINE       184
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T20,T25,T24
1	Covered	T1,T4,T5

 LINE       184
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T20,T25,T24
1	Not Covered

 LINE       184
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       198
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T5,T21

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	59	79.73
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	152	Covered	T2,T3,T8
AutoCaptGenCnt	139	Covered	T2,T3,T8
AutoCaptReseedCnt	137	Covered	T2,T3,T8
AutoDispatch	121	Covered	T2,T3,T8
AutoFirstAckWait	115	Covered	T2,T3,T8
AutoLoadIns	67	Covered	T2,T3,T8
AutoSendGenCmd	146	Covered	T2,T3,T8
AutoSendReseedCmd	158	Covered	T2,T3,T8
BootDone	94	Covered	T21,T22,T23
BootGenAckWait	86	Covered	T21,T22,T23
BootInsAckWait	77	Covered	T21,T24,T22
BootLoadGen	81	Covered	T21,T22,T23
BootLoadIns	63	Covered	T21,T24,T22
BootLoadUni	98	Covered	T26,T27,T28
BootPulse	90	Covered	T21,T22,T23
BootUniAckWait	103	Covered	T26,T27,T28
Error	184	Covered	T1,T4,T5
Idle	108	Covered	T1,T2,T3
RejectCsrngEntropy	184	Covered	T20,T25,T24
SWPortMode	72	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	127	Covered	T2,T3,T8
AutoAckWait->Error	184	Covered	T29,T30
AutoAckWait->Idle	208	Covered	T8,T31,T32
AutoAckWait->RejectCsrngEntropy	184	Covered	T25,T33,T34
AutoCaptGenCnt->AutoSendGenCmd	146	Covered	T2,T3,T8
AutoCaptGenCnt->Error	184	Covered	T5,T35,T36
AutoCaptGenCnt->Idle	208	Covered	T37,T38,T39
AutoCaptGenCnt->RejectCsrngEntropy	184	Not Covered
AutoCaptReseedCnt->AutoSendReseedCmd	158	Covered	T2,T3,T8
AutoCaptReseedCnt->Error	184	Covered	T40
AutoCaptReseedCnt->Idle	208	Covered	T8,T32,T41
AutoCaptReseedCnt->RejectCsrngEntropy	184	Not Covered
AutoDispatch->AutoCaptGenCnt	139	Covered	T2,T3,T8
AutoDispatch->AutoCaptReseedCnt	137	Covered	T2,T3,T8
AutoDispatch->Error	184	Covered	T42,T43,T44
AutoDispatch->Idle	134	Covered	T2,T3,T19
AutoDispatch->RejectCsrngEntropy	184	Not Covered
AutoFirstAckWait->AutoDispatch	121	Covered	T2,T3,T8
AutoFirstAckWait->Error	184	Covered	T45,T46
AutoFirstAckWait->Idle	208	Covered	T31,T47,T48
AutoFirstAckWait->RejectCsrngEntropy	184	Not Covered
AutoLoadIns->AutoFirstAckWait	115	Covered	T2,T3,T8
AutoLoadIns->Error	184	Covered	T7,T49,T50
AutoLoadIns->Idle	208	Covered	T5,T6,T7
AutoLoadIns->RejectCsrngEntropy	184	Not Covered
AutoSendGenCmd->AutoAckWait	152	Covered	T2,T3,T8
AutoSendGenCmd->Error	184	Covered	T51,T52,T53
AutoSendGenCmd->Idle	208	Covered	T54,T55,T56
AutoSendGenCmd->RejectCsrngEntropy	184	Not Covered
AutoSendReseedCmd->AutoAckWait	164	Covered	T2,T3,T8
AutoSendReseedCmd->Error	184	Covered	T57,T58
AutoSendReseedCmd->Idle	208	Covered	T59,T60,T61
AutoSendReseedCmd->RejectCsrngEntropy	184	Not Covered
BootDone->BootLoadUni	98	Covered	T26,T27,T28
BootDone->Error	184	Covered	T62
BootDone->Idle	208	Covered	T22,T63,T64
BootDone->RejectCsrngEntropy	184	Not Covered
BootGenAckWait->BootPulse	90	Covered	T21,T22,T23
BootGenAckWait->Error	184	Covered	T65,T66,T67
BootGenAckWait->Idle	208	Covered	T68,T69,T70
BootGenAckWait->RejectCsrngEntropy	184	Covered	T71,T72,T73
BootInsAckWait->BootLoadGen	81	Covered	T21,T22,T23
BootInsAckWait->Error	184	Covered	T22,T74,T75
BootInsAckWait->Idle	208	Covered	T23,T76,T77
BootInsAckWait->RejectCsrngEntropy	184	Covered	T24,T78,T79
BootLoadGen->BootGenAckWait	86	Covered	T21,T22,T23
BootLoadGen->Error	184	Not Covered
BootLoadGen->Idle	208	Covered	T21,T80,T81
BootLoadGen->RejectCsrngEntropy	184	Not Covered
BootLoadIns->BootInsAckWait	77	Covered	T21,T24,T22
BootLoadIns->Error	184	Covered	T68,T82,T83
BootLoadIns->Idle	208	Covered	T84,T85,T86
BootLoadIns->RejectCsrngEntropy	184	Not Covered
BootLoadUni->BootUniAckWait	103	Covered	T26,T27,T28
BootLoadUni->Error	184	Covered	T87,T88,T89
BootLoadUni->Idle	208	Not Covered
BootLoadUni->RejectCsrngEntropy	184	Not Covered
BootPulse->BootDone	94	Covered	T21,T22,T23
BootPulse->Error	184	Covered	T76,T77,T90
BootPulse->Idle	208	Covered	T91,T92,T93
BootPulse->RejectCsrngEntropy	184	Not Covered
BootUniAckWait->Error	184	Covered	T94,T95,T96
BootUniAckWait->Idle	108	Covered	T26,T27,T28
BootUniAckWait->RejectCsrngEntropy	184	Covered	T97,T98,T99
Idle->AutoLoadIns	67	Covered	T2,T3,T8
Idle->BootLoadIns	63	Covered	T21,T24,T22
Idle->Error	184	Covered	T4,T13,T14
Idle->RejectCsrngEntropy	184	Not Covered
Idle->SWPortMode	72	Covered	T1,T2,T3
RejectCsrngEntropy->Error	184	Covered	T20,T100,T101
RejectCsrngEntropy->Idle	208	Covered	T25,T24,T33
SWPortMode->Error	184	Covered	T1,T4,T12
SWPortMode->Idle	208	Covered	T4,T102,T103
SWPortMode->RejectCsrngEntropy	184	Covered	T20,T104,T100

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	41	2	2	100.00
CASE	60	35	35	100.00
IF	182	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if ((boot_req_mode_i && edn_enable_i))
-3-:	64	if ((auto_req_mode_i && edn_enable_i))
-4-:	68	if (edn_enable_i)
-5-:	80	if (csrng_cmd_ack_i)
-6-:	89	if (csrng_cmd_ack_i)
-7-:	97	if ((!boot_req_mode_i))
-8-:	106	if (csrng_cmd_ack_i)
-9-:	114	if (sw_cmd_req_load_i)
-10-:	120	if (csrng_cmd_ack_i)
-11-:	126	if (csrng_cmd_ack_i)
-12-:	132	if ((!auto_req_mode_i))
-13-:	136	if (max_reqs_cnt_zero_i)
-14-:	151	if (cmd_sent_i)
-15-:	163	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T24,T22
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T24,T22
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T24,T22
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T21,T24,T22
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T27,T28
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T26,T27,T28
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T26,T27,T28
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T3,T8
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T8
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T3,T8
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T3,T8
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T3,T19
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T3,T8
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T3,T8
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T3,T8
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T8
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T8
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T25,T24
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T23,T6

	LineNo.	Expression
-1-:	182	if ((local_escalate_i || csrng_ack_err_i))
-2-:	184	(local_escalate_i) ? 
-3-:	184	((state_q == Error)) ? 
-4-:	198	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T4,T5
1	0	1	-	Not Covered
1	0	0	-	Covered	T20,T25,T24
0	-	-	1	Covered	T8,T5,T21
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	176533014	139741	0	0
FpvSecCmErrorStEscalate_A	176533014	140778	0	0
u_state_regs_A	176502441	176337143	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176533014	139741	0	0
T1	1341	385	0	0
T2	6886	0	0	0
T3	1707	0	0	0
T4	50215	16857	0	0
T5	1250	600	0	0
T6	0	1060	0	0
T7	0	406	0	0
T8	2850	0	0	0
T12	0	380	0	0
T17	4312	0	0	0
T18	2986	0	0	0
T19	8033	0	0	0
T20	1124	600	0	0
T22	0	1118	0	0
T23	0	1060	0	0
T105	0	1132	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176533014	140778	0	0
T1	1341	386	0	0
T2	6886	0	0	0
T3	1707	0	0	0
T4	50215	17117	0	0
T5	1250	601	0	0
T6	0	1061	0	0
T7	0	407	0	0
T8	2850	0	0	0
T12	0	381	0	0
T17	4312	0	0	0
T18	2986	0	0	0
T19	8033	0	0	0
T20	1124	601	0	0
T22	0	1119	0	0
T23	0	1061	0	0
T105	0	1133	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176502441	176337143	0	0
T1	1188	1007	0	0
T2	6886	6834	0	0
T3	1707	1612	0	0
T4	50215	29274	0	0
T5	1037	884	0	0
T8	2850	2783	0	0
T17	4312	4240	0	0
T18	2986	2892	0	0
T19	8033	7955	0	0
T20	917	776	0	0