Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T112,T140,T141
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T113,T114,T115
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	352389644	1008302	0	0
DepthKnown_A	353066028	352735432	0	0
RvalidKnown_A	353066028	352735432	0	0
WreadyKnown_A	353066028	352735432	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	352749282	1084119	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352389644	1008302	0	0
T2	13772	7533	0	0
T3	3414	1222	0	0
T4	1830	0	0	0
T5	302	61	0	0
T8	5700	2540	0	0
T15	0	5705	0	0
T16	0	9473	0	0
T17	8624	0	0	0
T18	5972	0	0	0
T19	16066	11095	0	0
T20	158	0	0	0
T24	0	65	0	0
T25	0	480	0	0
T33	0	602	0	0
T102	485850	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	353066028	352735432	0	0
T1	2682	2320	0	0
T2	13772	13668	0	0
T3	3414	3224	0	0
T4	100430	58548	0	0
T5	2500	2194	0	0
T8	5700	5566	0	0
T17	8624	8480	0	0
T18	5972	5784	0	0
T19	16066	15910	0	0
T20	2248	1966	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	353066028	352735432	0	0
T1	2682	2320	0	0
T2	13772	13668	0	0
T3	3414	3224	0	0
T4	100430	58548	0	0
T5	2500	2194	0	0
T8	5700	5566	0	0
T17	8624	8480	0	0
T18	5972	5784	0	0
T19	16066	15910	0	0
T20	2248	1966	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	353066028	352735432	0	0
T1	2682	2320	0	0
T2	13772	13668	0	0
T3	3414	3224	0	0
T4	100430	58548	0	0
T5	2500	2194	0	0
T8	5700	5566	0	0
T17	8624	8480	0	0
T18	5972	5784	0	0
T19	16066	15910	0	0
T20	2248	1966	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	352749282	1084119	0	0
T2	13772	7533	0	0
T3	3414	1222	0	0
T4	1830	0	0	0
T5	2500	1032	0	0
T8	5700	2540	0	0
T15	0	5705	0	0
T16	0	9473	0	0
T17	8624	0	0	0
T18	5972	0	0	0
T19	16066	11095	0	0
T20	2248	398	0	0
T24	0	65	0	0
T25	0	480	0	0
T102	485850	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T142,T143
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T141
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T113,T114,T115
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	176194822	499484	0	0
DepthKnown_A	176533014	176367716	0	0
RvalidKnown_A	176533014	176367716	0	0
WreadyKnown_A	176533014	176367716	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	176374641	537190	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176194822	499484	0	0
T2	6886	3756	0	0
T3	1707	571	0	0
T4	915	0	0	0
T5	151	19	0	0
T8	2850	1260	0	0
T15	0	2829	0	0
T16	0	4734	0	0
T17	4312	0	0	0
T18	2986	0	0	0
T19	8033	5534	0	0
T20	79	0	0	0
T24	0	25	0	0
T25	0	234	0	0
T33	0	305	0	0
T102	242925	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176533014	176367716	0	0
T1	1341	1160	0	0
T2	6886	6834	0	0
T3	1707	1612	0	0
T4	50215	29274	0	0
T5	1250	1097	0	0
T8	2850	2783	0	0
T17	4312	4240	0	0
T18	2986	2892	0	0
T19	8033	7955	0	0
T20	1124	983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176533014	176367716	0	0
T1	1341	1160	0	0
T2	6886	6834	0	0
T3	1707	1612	0	0
T4	50215	29274	0	0
T5	1250	1097	0	0
T8	2850	2783	0	0
T17	4312	4240	0	0
T18	2986	2892	0	0
T19	8033	7955	0	0
T20	1124	983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176533014	176367716	0	0
T1	1341	1160	0	0
T2	6886	6834	0	0
T3	1707	1612	0	0
T4	50215	29274	0	0
T5	1250	1097	0	0
T8	2850	2783	0	0
T17	4312	4240	0	0
T18	2986	2892	0	0
T19	8033	7955	0	0
T20	1124	983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	176374641	537190	0	0
T2	6886	3756	0	0
T3	1707	571	0	0
T4	915	0	0	0
T5	1250	499	0	0
T8	2850	1260	0	0
T15	0	2829	0	0
T16	0	4734	0	0
T17	4312	0	0	0
T18	2986	0	0	0
T19	8033	5534	0	0
T20	1124	200	0	0
T24	0	25	0	0
T25	0	234	0	0
T102	242925	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T112,T140,T144
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T145
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	176194822	508818	0	0
DepthKnown_A	176533014	176367716	0	0
RvalidKnown_A	176533014	176367716	0	0
WreadyKnown_A	176533014	176367716	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	176374641	546929	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176194822	508818	0	0
T2	6886	3777	0	0
T3	1707	651	0	0
T4	915	0	0	0
T5	151	42	0	0
T8	2850	1280	0	0
T15	0	2876	0	0
T16	0	4739	0	0
T17	4312	0	0	0
T18	2986	0	0	0
T19	8033	5561	0	0
T20	79	0	0	0
T24	0	40	0	0
T25	0	246	0	0
T33	0	297	0	0
T102	242925	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176533014	176367716	0	0
T1	1341	1160	0	0
T2	6886	6834	0	0
T3	1707	1612	0	0
T4	50215	29274	0	0
T5	1250	1097	0	0
T8	2850	2783	0	0
T17	4312	4240	0	0
T18	2986	2892	0	0
T19	8033	7955	0	0
T20	1124	983	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176533014	176367716	0	0
T1	1341	1160	0	0
T2	6886	6834	0	0
T3	1707	1612	0	0
T4	50215	29274	0	0
T5	1250	1097	0	0
T8	2850	2783	0	0
T17	4312	4240	0	0
T18	2986	2892	0	0
T19	8033	7955	0	0
T20	1124	983	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176533014	176367716	0	0
T1	1341	1160	0	0
T2	6886	6834	0	0
T3	1707	1612	0	0
T4	50215	29274	0	0
T5	1250	1097	0	0
T8	2850	2783	0	0
T17	4312	4240	0	0
T18	2986	2892	0	0
T19	8033	7955	0	0
T20	1124	983	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	176374641	546929	0	0
T2	6886	3777	0	0
T3	1707	651	0	0
T4	915	0	0	0
T5	1250	533	0	0
T8	2850	1280	0	0
T15	0	2876	0	0
T16	0	4739	0	0
T17	4312	0	0	0
T18	2986	0	0	0
T19	8033	5561	0	0
T20	1124	198	0	0
T24	0	40	0	0
T25	0	246	0	0
T102	242925	0	0	0