Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	148	1			T23	1		T24	1		T26	1
auto_req_mode	131	1			T10	1		T12	1		T21	1
sw_mode	2856	1			T1	46		T3	1		T6	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

299

1

T23

1

T24

1

T44

1

single

100

1

T3

1

T26

1

T27

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1049	1			T6	1		T4	2		T23	1
auto[2]	133	1			T44	1		T178	58		T272	1
auto[3]	96	1			T273	1		T219	38		T274	1
auto[4]	124	1			T275	1		T276	1		T277	1
auto[5]	304	1			T5	12		T48	1		T278	1
auto[6]	107	1			T279	1		T280	1		T250	1
auto[7]	1322	1			T1	46		T3	1		T10	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[6]]	[auto_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	83	1			T23	1		T24	1		T26	1
auto[1]	auto_req_mode	80	1			T12	1		T22	1		T75	1
auto[1]	sw_mode	886	1			T6	1		T4	2		T25	1
auto[2]	boot_req_mode	1	1			T281	1		-	-		-	-
auto[2]	auto_req_mode	3	1			T282	1		T283	1		T284	1
auto[2]	sw_mode	129	1			T44	1		T178	58		T272	1
auto[3]	boot_req_mode	1	1			T285	1		-	-		-	-
auto[3]	auto_req_mode	2	1			T286	1		T287	1		-	-
auto[3]	sw_mode	93	1			T273	1		T219	38		T274	1
auto[4]	boot_req_mode	2	1			T277	1		T288	1		-	-
auto[4]	auto_req_mode	1	1			T275	1		-	-		-	-
auto[4]	sw_mode	121	1			T276	1		T289	5		T290	38
auto[5]	boot_req_mode	7	1			T48	1		T291	1		T292	1
auto[5]	auto_req_mode	2	1			T278	1		T15	1		-	-
auto[5]	sw_mode	295	1			T5	12		T293	1		T294	1
auto[6]	boot_req_mode	6	1			T279	1		T280	1		T295	1
auto[6]	sw_mode	101	1			T250	1		T296	1		T297	1
auto[7]	boot_req_mode	48	1			T46	1		T49	1		T52	1
auto[7]	auto_req_mode	43	1			T10	1		T21	1		T71	1
auto[7]	sw_mode	1231	1			T1	46		T3	1		T45	1