Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	693457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5659764

1

T1

163294

T2

4

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1673347	1			T1	46306		T2	1		T3	61
values[0x0]	2163922	1			T1	62293		T2	14		T3	17
values[0x1]	2515952	1			T1	72768		T2	13		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	342080	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6011141

1

T1

172850

T2

6

T3

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24322	1			T1	725		T5	1		T12	1
valid_sources[0x01]	25052	1			T1	691		T3	17		T4	2
valid_sources[0x02]	25848	1			T1	767		T4	2		T23	1
valid_sources[0x03]	26262	1			T1	705		T4	2		T24	1
valid_sources[0x04]	24564	1			T1	753		T4	1		T23	2
valid_sources[0x05]	24788	1			T1	664		T23	1		T24	1
valid_sources[0x06]	24528	1			T1	663		T6	3		T23	1
valid_sources[0x07]	25413	1			T1	694		T4	2		T24	1
valid_sources[0x08]	24732	1			T1	695		T4	2		T5	1
valid_sources[0x09]	24829	1			T1	709		T2	2		T3	10
valid_sources[0x0a]	24882	1			T1	693		T5	8		T46	1
valid_sources[0x0b]	22826	1			T1	711		T4	1		T10	1
valid_sources[0x0c]	24315	1			T1	732		T10	3		T12	1
valid_sources[0x0d]	24779	1			T1	690		T23	1		T24	1
valid_sources[0x0e]	25626	1			T1	688		T6	3		T4	4
valid_sources[0x0f]	26713	1			T1	686		T2	1		T4	3
valid_sources[0x10]	25918	1			T1	661		T23	2		T24	1
valid_sources[0x11]	25637	1			T1	752		T4	1		T46	1
valid_sources[0x12]	24919	1			T1	687		T5	7		T16	1
valid_sources[0x13]	27167	1			T1	693		T24	1		T5	1
valid_sources[0x14]	25116	1			T1	735		T4	1		T24	1
valid_sources[0x15]	24875	1			T1	706		T23	1		T24	2
valid_sources[0x16]	25613	1			T1	674		T2	2		T23	2
valid_sources[0x17]	24253	1			T1	738		T3	12		T44	3
valid_sources[0x18]	24760	1			T1	684		T6	6		T4	2
valid_sources[0x19]	24774	1			T1	715		T5	5		T10	2
valid_sources[0x1a]	23489	1			T1	740		T24	1		T5	1
valid_sources[0x1b]	26097	1			T1	730		T4	1		T23	1
valid_sources[0x1c]	23801	1			T1	750		T24	1		T5	3
valid_sources[0x1d]	24838	1			T1	748		T2	1		T4	2
valid_sources[0x1e]	24404	1			T1	716		T4	1		T24	3
valid_sources[0x1f]	23179	1			T1	687		T4	3		T23	1
valid_sources[0x20]	23827	1			T1	732		T4	1		T23	1
valid_sources[0x21]	24970	1			T1	686		T4	1		T5	8
valid_sources[0x22]	25887	1			T1	734		T4	2		T24	1
valid_sources[0x23]	24674	1			T1	721		T4	2		T23	1
valid_sources[0x24]	26302	1			T1	698		T4	1		T5	1
valid_sources[0x25]	23937	1			T1	689		T5	5		T10	1
valid_sources[0x26]	24683	1			T1	699		T24	1		T27	8
valid_sources[0x27]	26007	1			T1	683		T4	1		T23	1
valid_sources[0x28]	24829	1			T1	702		T4	3		T10	2
valid_sources[0x29]	25120	1			T1	739		T2	3		T4	2
valid_sources[0x2a]	24189	1			T1	681		T24	1		T5	9
valid_sources[0x2b]	23340	1			T1	670		T24	3		T64	1
valid_sources[0x2c]	24558	1			T1	705		T4	1		T23	3
valid_sources[0x2d]	24036	1			T1	676		T6	12		T4	1
valid_sources[0x2e]	25840	1			T1	695		T4	3		T23	4
valid_sources[0x2f]	24047	1			T1	697		T4	2		T23	1
valid_sources[0x30]	23779	1			T1	718		T4	1		T23	1
valid_sources[0x31]	26837	1			T1	752		T4	1		T23	2
valid_sources[0x32]	24685	1			T1	728		T23	1		T24	3
valid_sources[0x33]	25084	1			T1	721		T24	3		T5	7
valid_sources[0x34]	25714	1			T1	711		T23	2		T24	2
valid_sources[0x35]	25122	1			T1	753		T2	2		T4	1
valid_sources[0x36]	25160	1			T1	687		T2	3		T23	1
valid_sources[0x37]	24808	1			T1	691		T4	3		T24	1
valid_sources[0x38]	25344	1			T1	697		T4	2		T24	2
valid_sources[0x39]	23904	1			T1	695		T2	1		T4	3
valid_sources[0x3a]	23655	1			T1	710		T4	2		T23	2
valid_sources[0x3b]	25276	1			T1	639		T4	2		T23	3
valid_sources[0x3c]	23476	1			T1	696		T4	1		T25	2
valid_sources[0x3d]	25963	1			T1	730		T4	2		T44	3
valid_sources[0x3e]	23963	1			T1	720		T23	2		T5	7
valid_sources[0x3f]	23606	1			T1	731		T5	2		T11	5
valid_sources[0x40]	24240	1			T1	709		T23	2		T24	1
valid_sources[0x41]	26115	1			T1	662		T4	2		T64	5
valid_sources[0x42]	26662	1			T1	710		T24	1		T64	1
valid_sources[0x43]	23948	1			T1	686		T24	1		T5	3
valid_sources[0x44]	24650	1			T1	696		T4	4		T24	1
valid_sources[0x45]	26742	1			T1	687		T2	1		T24	1
valid_sources[0x46]	25115	1			T1	685		T24	1		T5	4
valid_sources[0x47]	26396	1			T1	730		T4	2		T5	6
valid_sources[0x48]	24110	1			T1	706		T4	1		T24	1
valid_sources[0x49]	24307	1			T1	726		T5	5		T46	1
valid_sources[0x4a]	25802	1			T1	720		T4	1		T5	1
valid_sources[0x4b]	24720	1			T1	750		T4	3		T24	5
valid_sources[0x4c]	24122	1			T1	677		T23	5		T24	2
valid_sources[0x4d]	25880	1			T1	704		T4	2		T24	1
valid_sources[0x4e]	26306	1			T1	691		T6	2		T24	1
valid_sources[0x4f]	25171	1			T1	699		T5	3		T11	2
valid_sources[0x50]	24799	1			T1	702		T4	2		T23	2
valid_sources[0x51]	27080	1			T1	679		T24	1		T5	1
valid_sources[0x52]	25655	1			T1	738		T4	2		T44	2
valid_sources[0x53]	24490	1			T1	628		T4	3		T23	2
valid_sources[0x54]	24896	1			T1	714		T4	1		T24	1
valid_sources[0x55]	24061	1			T1	663		T4	1		T10	1
valid_sources[0x56]	26618	1			T1	712		T4	2		T27	3
valid_sources[0x57]	25067	1			T1	717		T6	5		T4	1
valid_sources[0x58]	23823	1			T1	694		T4	2		T25	1
valid_sources[0x59]	23842	1			T1	746		T25	1		T64	4
valid_sources[0x5a]	24497	1			T1	677		T4	1		T23	4
valid_sources[0x5b]	24447	1			T1	729		T4	1		T24	1
valid_sources[0x5c]	24494	1			T1	706		T4	1		T24	3
valid_sources[0x5d]	25008	1			T1	720		T2	1		T4	1
valid_sources[0x5e]	26337	1			T1	703		T23	1		T24	2
valid_sources[0x5f]	26591	1			T1	772		T4	2		T23	1
valid_sources[0x60]	25320	1			T1	740		T4	2		T24	1
valid_sources[0x61]	24586	1			T1	691		T4	1		T23	2
valid_sources[0x62]	23179	1			T1	709		T4	1		T23	2
valid_sources[0x63]	24856	1			T1	681		T4	1		T44	1
valid_sources[0x64]	25198	1			T1	745		T5	2		T10	1
valid_sources[0x65]	25389	1			T1	730		T5	2		T10	2
valid_sources[0x66]	24887	1			T1	781		T4	1		T5	13
valid_sources[0x67]	23660	1			T1	737		T4	3		T24	1
valid_sources[0x68]	25719	1			T1	663		T4	1		T23	1
valid_sources[0x69]	24106	1			T1	698		T4	1		T24	1
valid_sources[0x6a]	24236	1			T1	747		T23	1		T24	1
valid_sources[0x6b]	23973	1			T1	699		T23	1		T5	4
valid_sources[0x6c]	26283	1			T1	715		T5	2		T46	1
valid_sources[0x6d]	24044	1			T1	654		T4	1		T5	8
valid_sources[0x6e]	25183	1			T1	751		T4	1		T27	3
valid_sources[0x6f]	24335	1			T1	686		T24	1		T27	1
valid_sources[0x70]	23399	1			T1	662		T5	6		T46	1
valid_sources[0x71]	24907	1			T1	752		T4	1		T24	1
valid_sources[0x72]	24148	1			T1	701		T4	5		T5	3
valid_sources[0x73]	24017	1			T1	724		T4	1		T24	2
valid_sources[0x74]	24882	1			T1	741		T3	41		T4	1
valid_sources[0x75]	24180	1			T1	715		T4	1		T5	5
valid_sources[0x76]	24508	1			T1	717		T6	6		T4	2
valid_sources[0x77]	26932	1			T1	655		T24	1		T5	1
valid_sources[0x78]	24340	1			T1	676		T4	4		T24	1
valid_sources[0x79]	24555	1			T1	672		T4	2		T23	2
valid_sources[0x7a]	24580	1			T1	740		T5	1		T46	1
valid_sources[0x7b]	24706	1			T1	721		T4	1		T23	2
valid_sources[0x7c]	24814	1			T1	731		T4	2		T5	2
valid_sources[0x7d]	24656	1			T1	702		T4	1		T23	1
valid_sources[0x7e]	25943	1			T1	710		T4	1		T5	2
valid_sources[0x7f]	25017	1			T1	692		T2	1		T23	4
valid_sources[0x80]	25165	1			T1	701		T4	1		T24	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1425144

1

T1

40895

T3

5

T6

4

values[0x0]

all_enables

biggest_size

2119216

1

T1

61126

T2

3

T3

14

values[0x1]

all_enables

biggest_size

2115404

1

T1

61273

T2

1

T3

14