Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
60.94	60.94	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	60.94	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.94	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	25	27	51.92

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	25	27	51.92	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2629	1			T1	48		T4	2		T23	1
non_zero_bins[1]	1901	1			T1	24		T3	3		T4	1
zero	8453	1			T1	100		T3	1		T6	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	523	1			T1	11		T3	1		T23	1
uni	3641	1			T1	53		T3	1		T6	1
gen	3910	1			T1	46		T3	1		T6	1
res	826	1			T1	8		T4	1		T27	1
ins	4083	1			T1	54		T3	1		T6	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8759

1

T1

111

T3

2

T6

3

mubi_true

4224

1

T1

61

T3

2

T4

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

5

1

T86

1

T129

1

T130

1

pass

12978

1

T1

172

T3

4

T6

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	25	27	51.92	25
Automatically Generated Cross Bins	52	25	27	51.92	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4
[res , ins]	*	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen]	[zero]	[fail]	[mubi_true]	0	1	1

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	106	1			T1	5		T5	1		T46	1
upd	non_zero_bins[0]	pass	mubi_true	135	1			T1	4		T44	1		T5	1
upd	non_zero_bins[1]	pass	mubi_false	78	1			T3	1		T42	2		T61	1
upd	non_zero_bins[1]	pass	mubi_true	98	1			T1	1		T68	1		T43	2
upd	zero	pass	mubi_false	59	1			T23	1		T42	1		T260	1
upd	zero	pass	mubi_true	47	1			T1	1		T61	2		T43	1
uni	zero	pass	mubi_false	2713	1			T1	40		T3	1		T6	1
uni	zero	pass	mubi_true	928	1			T1	13		T24	1		T25	1
gen	non_zero_bins[0]	pass	mubi_false	479	1			T1	9		T23	1		T24	1
gen	non_zero_bins[0]	pass	mubi_true	489	1			T1	3		T44	1		T5	3
gen	non_zero_bins[1]	pass	mubi_false	366	1			T1	6		T27	1		T5	1
gen	non_zero_bins[1]	pass	mubi_true	363	1			T1	3		T3	1		T4	1
gen	zero	fail	mubi_false	5	1			T86	1		T129	1		T130	1
gen	zero	pass	mubi_false	1800	1			T1	21		T6	1		T4	1
gen	zero	pass	mubi_true	408	1			T1	4		T23	1		T24	1
res	non_zero_bins[0]	pass	mubi_false	188	1			T1	1		T42	4		T61	1
res	non_zero_bins[0]	pass	mubi_true	203	1			T1	6		T4	1		T5	1
res	non_zero_bins[1]	pass	mubi_false	124	1			T5	1		T42	3		T21	2
res	non_zero_bins[1]	pass	mubi_true	124	1			T1	1		T42	2		T65	2
res	zero	pass	mubi_false	93	1			T27	1		T64	1		T43	1
res	zero	pass	mubi_true	94	1			T5	1		T10	2		T64	2
ins	non_zero_bins[0]	pass	mubi_false	487	1			T1	5		T5	1		T46	1
ins	non_zero_bins[0]	pass	mubi_true	542	1			T1	15		T4	1		T24	2
ins	non_zero_bins[1]	pass	mubi_false	361	1			T1	6		T5	2		T12	1
ins	non_zero_bins[1]	pass	mubi_true	387	1			T1	7		T3	1		T23	1
ins	zero	pass	mubi_false	1900	1			T1	18		T6	1		T4	1
ins	zero	pass	mubi_true	406	1			T1	3		T68	1		T11	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded