Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T26,T17,T36
1	1	Covered	T23,T24,T26

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T12,T7,T73
1	1	Covered	T10,T11,T12

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T31,T32
1	0	Covered	T16,T17,T36

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T11,T31,T32
1	Covered	T16,T17,T36

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T11,T31,T32
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T11,T16,T17
1	Covered	T16,T17,T36

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T11,T12

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T10,T11,T12
AutoCaptGenCnt	143	Covered	T10,T11,T12
AutoCaptReseedCnt	141	Covered	T10,T11,T12
AutoDispatch	125	Covered	T10,T11,T12
AutoFirstAckWait	119	Covered	T10,T11,T12
AutoLoadIns	69	Covered	T10,T11,T12
AutoSendGenCmd	150	Covered	T10,T11,T12
AutoSendReseedCmd	162	Covered	T10,T12,T21
BootDone	98	Covered	T23,T24,T26
BootGenAckWait	90	Covered	T23,T24,T26
BootInsAckWait	80	Covered	T23,T24,T26
BootLoadGen	85	Covered	T23,T24,T26
BootLoadIns	65	Covered	T23,T24,T26
BootLoadUni	102	Covered	T23,T24,T27
BootPulse	94	Covered	T23,T24,T26
BootUniAckWait	107	Covered	T23,T24,T27
Error	188	Covered	T16,T17,T36
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T11,T31,T32
SWPortMode	74	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T10,T11,T12
AutoAckWait->Error	188	Covered	T8,T95
AutoAckWait->Idle	211	Covered	T12,T73,T76
AutoAckWait->RejectCsrngEntropy	188	Covered	T96
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T10,T11,T12
AutoCaptGenCnt->Error	188	Covered	T97
AutoCaptGenCnt->Idle	211	Covered	T98,T99,T100
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T101,T88,T102
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T10,T12,T21
AutoCaptReseedCnt->Error	188	Covered	T103,T104,T105
AutoCaptReseedCnt->Idle	211	Covered	T106,T107,T108
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T11,T32,T87
AutoDispatch->AutoCaptGenCnt	143	Covered	T10,T11,T12
AutoDispatch->AutoCaptReseedCnt	141	Covered	T10,T11,T12
AutoDispatch->Error	188	Covered	T109,T110
AutoDispatch->Idle	138	Covered	T10,T21,T22
AutoDispatch->RejectCsrngEntropy	188	Covered	T54
AutoFirstAckWait->AutoDispatch	125	Covered	T10,T11,T12
AutoFirstAckWait->Error	188	Covered	T111,T112,T113
AutoFirstAckWait->Idle	211	Covered	T114,T115,T116
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T117,T118
AutoLoadIns->AutoFirstAckWait	119	Covered	T10,T11,T12
AutoLoadIns->Error	188	Covered	T119,T120,T121
AutoLoadIns->Idle	211	Covered	T11,T12,T7
AutoLoadIns->RejectCsrngEntropy	188	Covered	T122,T123,T124
AutoSendGenCmd->AutoAckWait	156	Covered	T10,T11,T12
AutoSendGenCmd->Error	188	Covered	T125,T59,T126
AutoSendGenCmd->Idle	211	Covered	T76,T127,T128
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T86,T129,T130
AutoSendReseedCmd->AutoAckWait	168	Covered	T10,T12,T21
AutoSendReseedCmd->Error	188	Covered	T131
AutoSendReseedCmd->Idle	211	Covered	T132,T133,T134
AutoSendReseedCmd->RejectCsrngEntropy	188	Not Covered
BootDone->BootLoadUni	102	Covered	T23,T24,T27
BootDone->Error	188	Covered	T56,T57,T135
BootDone->Idle	211	Covered	T136,T137,T138
BootDone->RejectCsrngEntropy	188	Covered	T139
BootGenAckWait->BootPulse	94	Covered	T23,T24,T26
BootGenAckWait->Error	188	Covered	T17,T55,T140
BootGenAckWait->Idle	211	Covered	T141,T142,T143
BootGenAckWait->RejectCsrngEntropy	188	Covered	T82,T144,T145
BootInsAckWait->BootLoadGen	85	Covered	T23,T24,T26
BootInsAckWait->Error	188	Covered	T36,T18,T143
BootInsAckWait->Idle	211	Covered	T17,T36,T18
BootInsAckWait->RejectCsrngEntropy	188	Covered	T83,T84,T89
BootLoadGen->BootGenAckWait	90	Covered	T23,T24,T26
BootLoadGen->Error	188	Covered	T146,T147,T148
BootLoadGen->Idle	211	Covered	T149,T150,T151
BootLoadGen->RejectCsrngEntropy	188	Covered	T152,T153,T154
BootLoadIns->BootInsAckWait	80	Covered	T23,T24,T26
BootLoadIns->Error	188	Covered	T155,T156
BootLoadIns->Idle	211	Covered	T157,T158,T159
BootLoadIns->RejectCsrngEntropy	188	Covered	T31,T160,T161
BootLoadUni->BootUniAckWait	107	Covered	T23,T24,T27
BootLoadUni->Error	188	Covered	T162
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T163
BootPulse->BootDone	98	Covered	T23,T24,T26
BootPulse->Error	188	Covered	T164,T165,T166
BootPulse->Idle	211	Covered	T26,T167,T168
BootPulse->RejectCsrngEntropy	188	Covered	T169
BootUniAckWait->Error	188	Covered	T170,T171
BootUniAckWait->Idle	112	Covered	T23,T24,T27
BootUniAckWait->RejectCsrngEntropy	188	Covered	T85
Idle->AutoLoadIns	69	Covered	T10,T11,T12
Idle->BootLoadIns	65	Covered	T23,T24,T26
Idle->Error	188	Covered	T16,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T82,T83,T85
Idle->SWPortMode	74	Covered	T1,T3,T6
RejectCsrngEntropy->Error	188	Covered	T53,T172,T173
RejectCsrngEntropy->Idle	211	Covered	T11,T31,T32
SWPortMode->Error	188	Covered	T16,T174,T175
SWPortMode->Idle	211	Covered	T1,T4,T5
SWPortMode->RejectCsrngEntropy	188	Covered	T11,T31,T32

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T26
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T26
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T26
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T26
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T26
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T26
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T26
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T26
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T24,T27
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T26,T17,T36
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T27
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T23,T24,T27
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T23,T24,T27
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T11,T12
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T10,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T10,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T21,T22
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T10,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T10,T11,T12
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T11,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T10,T11,T12
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T12,T21
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T12,T21
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T31,T32
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T36
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T9

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T16,T17,T36
1	0	1	-	Not Covered
1	0	0	-	Covered	T11,T31,T32
0	-	-	1	Covered	T26,T11,T12
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	221079372	152006	0	0
FpvSecCmErrorStEscalate_A	221079372	153049	0	0
u_state_regs_A	221038299	220870321	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	152006	0	0
T7	0	1060	0	0
T8	0	194	0	0
T9	0	612	0	0
T16	46398	18152	0	0
T17	1907	1102	0	0
T18	0	661	0	0
T21	4559	0	0	0
T36	1056	600	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	352	0	0
T56	0	362	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	390	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	153049	0	0
T7	0	1061	0	0
T8	0	195	0	0
T9	0	613	0	0
T16	46398	18412	0	0
T17	1907	1103	0	0
T18	0	662	0	0
T21	4559	0	0	0
T36	1056	601	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	353	0	0
T56	0	363	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	391	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221038299	220870321	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0