Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T11,T12

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T6
DataWait	75	Covered	T1,T3,T6
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T6
Error	99	Covered	T16,T17,T36
Idle	68	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T176,T167,T177
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T6
DataWait->AckPls	80	Covered	T1,T3,T6
DataWait->Disabled	107	Covered	T149,T178,T76
DataWait->Error	99	Covered	T17,T7,T8
Disabled->EndPointClear	63	Covered	T1,T3,T6
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T4,T12,T64
EndPointClear->Error	99	Covered	T16,T19,T20
EndPointClear->Idle	68	Covered	T1,T3,T6
Idle->DataWait	75	Covered	T1,T3,T6
Idle->Disabled	107	Covered	T1,T4,T26
Idle->Error	99	Covered	T17,T36,T7

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T6
Idle	-	1	1	-	Covered	T1,T3,T6
Idle	-	1	0	-	Covered	T1,T3,T6
Idle	-	0	-	-	Covered	T1,T3,T6
DataWait	-	-	-	1	Covered	T1,T3,T6
DataWait	-	-	-	0	Covered	T1,T3,T6
AckPls	-	-	-	-	Covered	T1,T3,T6
Error	-	-	-	-	Covered	T16,T17,T36
default	-	-	-	-	Covered	T16,T36,T8

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T17,T36
0	1	Covered	T26,T11,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1547555604	1076392	0	0
FpvSecCmErrorStEscalate_A	1547555604	1083693	0	0
u_state_regs_A	1547514531	1546338685	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547555604	1076392	0	0
T7	0	7770	0	0
T8	0	1308	0	0
T9	0	4634	0	0
T16	324786	127064	0	0
T17	13349	7714	0	0
T18	0	4627	0	0
T21	31913	0	0	0
T36	7392	4150	0	0
T42	1376004	0	0	0
T45	29372	0	0	0
T47	19719	0	0	0
T51	15617	0	0	0
T55	0	2464	0	0
T56	0	2534	0	0
T60	10458	0	0	0
T61	92477	0	0	0
T174	0	2680	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547555604	1083693	0	0
T7	0	7777	0	0
T8	0	1315	0	0
T9	0	4641	0	0
T16	324786	128884	0	0
T17	13349	7721	0	0
T18	0	4634	0	0
T21	31913	0	0	0
T36	7392	4157	0	0
T42	1376004	0	0	0
T45	29372	0	0	0
T47	19719	0	0	0
T51	15617	0	0	0
T55	0	2471	0	0
T56	0	2541	0	0
T60	10458	0	0	0
T61	92477	0	0	0
T174	0	2687	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547514531	1546338685	0	0
T1	3651207	3651109	0	0
T2	11613	11137	0	0
T3	15463	14798	0	0
T4	36841	34951	0	0
T6	8911	8470	0	0
T23	25900	25312	0	0
T24	26159	25662	0	0
T25	6237	5810	0	0
T26	4809	4438	0	0
T27	27951	27377	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T11,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T44,T12
DataWait	75	Covered	T3,T44,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T6
Error	99	Covered	T16,T17,T36
Idle	68	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T167,T179
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T44,T12
DataWait->AckPls	80	Covered	T3,T44,T12
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T8,T170,T146
Disabled->EndPointClear	63	Covered	T1,T3,T6
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T4,T12,T64
EndPointClear->Error	99	Covered	T16,T19,T20
EndPointClear->Idle	68	Covered	T1,T3,T6
Idle->DataWait	75	Covered	T3,T44,T12
Idle->Disabled	107	Covered	T1,T4,T26
Idle->Error	99	Covered	T17,T36,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T6
Idle	-	1	1	-	Covered	T3,T44,T12
Idle	-	1	0	-	Covered	T3,T44,T12
Idle	-	0	-	-	Covered	T1,T3,T6
DataWait	-	-	-	1	Covered	T3,T44,T12
DataWait	-	-	-	0	Covered	T3,T44,T12
AckPls	-	-	-	-	Covered	T3,T44,T12
Error	-	-	-	-	Covered	T16,T17,T36
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T17,T36
0	1	Covered	T26,T11,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221079372	154106	0	0
FpvSecCmErrorStEscalate_A	221079372	155149	0	0
u_state_regs_A	221079372	220911394	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	154106	0	0
T7	0	1110	0	0
T8	0	194	0	0
T9	0	662	0	0
T16	46398	18152	0	0
T17	1907	1102	0	0
T18	0	661	0	0
T21	4559	0	0	0
T36	1056	600	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	352	0	0
T56	0	362	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	390	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	155149	0	0
T7	0	1111	0	0
T8	0	195	0	0
T9	0	663	0	0
T16	46398	18412	0	0
T17	1907	1103	0	0
T18	0	662	0	0
T21	4559	0	0	0
T36	1056	601	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	353	0	0
T56	0	363	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	391	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T11,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T10,T11
DataWait	75	Covered	T3,T10,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T6
Error	99	Covered	T16,T17,T36
Idle	68	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T10,T11
DataWait->AckPls	80	Covered	T3,T10,T11
DataWait->Disabled	107	Covered	T149,T150,T180
DataWait->Error	99	Covered	T17,T57,T143
Disabled->EndPointClear	63	Covered	T1,T3,T6
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T4,T12,T64
EndPointClear->Error	99	Covered	T16,T19,T20
EndPointClear->Idle	68	Covered	T1,T3,T6
Idle->DataWait	75	Covered	T3,T10,T11
Idle->Disabled	107	Covered	T1,T4,T26
Idle->Error	99	Covered	T36,T7,T18

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T6
Idle	-	1	1	-	Covered	T3,T10,T11
Idle	-	1	0	-	Covered	T3,T10,T11
Idle	-	0	-	-	Covered	T1,T3,T6
DataWait	-	-	-	1	Covered	T3,T10,T11
DataWait	-	-	-	0	Covered	T3,T10,T11
AckPls	-	-	-	-	Covered	T3,T10,T11
Error	-	-	-	-	Covered	T16,T17,T36
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T17,T36
0	1	Covered	T26,T11,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221079372	154106	0	0
FpvSecCmErrorStEscalate_A	221079372	155149	0	0
u_state_regs_A	221079372	220911394	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	154106	0	0
T7	0	1110	0	0
T8	0	194	0	0
T9	0	662	0	0
T16	46398	18152	0	0
T17	1907	1102	0	0
T18	0	661	0	0
T21	4559	0	0	0
T36	1056	600	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	352	0	0
T56	0	362	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	390	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	155149	0	0
T7	0	1111	0	0
T8	0	195	0	0
T9	0	663	0	0
T16	46398	18412	0	0
T17	1907	1103	0	0
T18	0	662	0	0
T21	4559	0	0	0
T36	1056	601	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	353	0	0
T56	0	363	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	391	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T11,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T46,T45,T47
DataWait	75	Covered	T46,T45,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T6
Error	99	Covered	T16,T17,T36
Idle	68	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T46,T45,T47
DataWait->AckPls	80	Covered	T46,T45,T47
DataWait->Disabled	107	Covered	T98,T181,T182
DataWait->Error	99	Covered	T164,T183,T184
Disabled->EndPointClear	63	Covered	T1,T3,T6
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T4,T12,T64
EndPointClear->Error	99	Covered	T16,T19,T20
EndPointClear->Idle	68	Covered	T1,T3,T6
Idle->DataWait	75	Covered	T46,T45,T47
Idle->Disabled	107	Covered	T1,T4,T26
Idle->Error	99	Covered	T17,T36,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T6
Idle	-	1	1	-	Covered	T46,T45,T47
Idle	-	1	0	-	Covered	T46,T45,T47
Idle	-	0	-	-	Covered	T1,T3,T6
DataWait	-	-	-	1	Covered	T46,T45,T47
DataWait	-	-	-	0	Covered	T46,T45,T47
AckPls	-	-	-	-	Covered	T46,T45,T47
Error	-	-	-	-	Covered	T16,T17,T36
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T17,T36
0	1	Covered	T26,T11,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221079372	154106	0	0
FpvSecCmErrorStEscalate_A	221079372	155149	0	0
u_state_regs_A	221079372	220911394	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	154106	0	0
T7	0	1110	0	0
T8	0	194	0	0
T9	0	662	0	0
T16	46398	18152	0	0
T17	1907	1102	0	0
T18	0	661	0	0
T21	4559	0	0	0
T36	1056	600	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	352	0	0
T56	0	362	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	390	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	155149	0	0
T7	0	1111	0	0
T8	0	195	0	0
T9	0	663	0	0
T16	46398	18412	0	0
T17	1907	1103	0	0
T18	0	662	0	0
T21	4559	0	0	0
T36	1056	601	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	353	0	0
T56	0	363	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	391	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T11,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T26,T46,T45
DataWait	75	Covered	T26,T46,T45
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T6
Error	99	Covered	T16,T17,T36
Idle	68	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T26,T46,T45
DataWait->AckPls	80	Covered	T26,T46,T45
DataWait->Disabled	107	Covered	T151,T185,T186
DataWait->Error	99	Covered	T111,T187,T188
Disabled->EndPointClear	63	Covered	T1,T3,T6
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T4,T12,T64
EndPointClear->Error	99	Covered	T16,T19,T20
EndPointClear->Idle	68	Covered	T1,T3,T6
Idle->DataWait	75	Covered	T26,T46,T45
Idle->Disabled	107	Covered	T1,T4,T26
Idle->Error	99	Covered	T17,T36,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T6
Idle	-	1	1	-	Covered	T26,T46,T45
Idle	-	1	0	-	Covered	T26,T46,T45
Idle	-	0	-	-	Covered	T1,T3,T6
DataWait	-	-	-	1	Covered	T26,T46,T45
DataWait	-	-	-	0	Covered	T26,T46,T45
AckPls	-	-	-	-	Covered	T26,T46,T45
Error	-	-	-	-	Covered	T16,T17,T36
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T17,T36
0	1	Covered	T26,T11,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221079372	154106	0	0
FpvSecCmErrorStEscalate_A	221079372	155149	0	0
u_state_regs_A	221079372	220911394	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	154106	0	0
T7	0	1110	0	0
T8	0	194	0	0
T9	0	662	0	0
T16	46398	18152	0	0
T17	1907	1102	0	0
T18	0	661	0	0
T21	4559	0	0	0
T36	1056	600	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	352	0	0
T56	0	362	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	390	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	155149	0	0
T7	0	1111	0	0
T8	0	195	0	0
T9	0	663	0	0
T16	46398	18412	0	0
T17	1907	1103	0	0
T18	0	662	0	0
T21	4559	0	0	0
T36	1056	601	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	353	0	0
T56	0	363	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	391	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T11,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T6,T4
DataWait	75	Covered	T1,T6,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T6
Error	99	Covered	T16,T17,T36
Idle	68	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T189
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T6,T4
DataWait->AckPls	80	Covered	T1,T6,T4
DataWait->Disabled	107	Covered	T178,T76,T127
DataWait->Error	99	Covered	T7,T55,T9
Disabled->EndPointClear	63	Covered	T1,T3,T6
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T4,T12,T64
EndPointClear->Error	99	Covered	T16,T19,T20
EndPointClear->Idle	68	Covered	T1,T3,T6
Idle->DataWait	75	Covered	T1,T6,T4
Idle->Disabled	107	Covered	T1,T4,T26
Idle->Error	99	Covered	T17,T18,T190

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T6
Idle	-	1	1	-	Covered	T1,T6,T4
Idle	-	1	0	-	Covered	T1,T6,T4
Idle	-	0	-	-	Covered	T1,T3,T6
DataWait	-	-	-	1	Covered	T1,T6,T4
DataWait	-	-	-	0	Covered	T1,T6,T4
AckPls	-	-	-	-	Covered	T1,T6,T4
Error	-	-	-	-	Covered	T16,T17,T36
default	-	-	-	-	Covered	T16,T36,T8

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T17,T36
0	1	Covered	T26,T11,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221079372	151756	0	0
FpvSecCmErrorStEscalate_A	221079372	152799	0	0
u_state_regs_A	221038299	220870321	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	151756	0	0
T7	0	1110	0	0
T8	0	144	0	0
T9	0	662	0	0
T16	46398	18152	0	0
T17	1907	1102	0	0
T18	0	661	0	0
T21	4559	0	0	0
T36	1056	550	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	352	0	0
T56	0	362	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	340	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	152799	0	0
T7	0	1111	0	0
T8	0	145	0	0
T9	0	663	0	0
T16	46398	18412	0	0
T17	1907	1103	0	0
T18	0	662	0	0
T21	4559	0	0	0
T36	1056	551	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	353	0	0
T56	0	363	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	341	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221038299	220870321	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T11,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T45,T47
DataWait	75	Covered	T10,T45,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T6
Error	99	Covered	T16,T17,T36
Idle	68	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T176
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T45,T47
DataWait->AckPls	80	Covered	T10,T45,T47
DataWait->Disabled	107	Covered	T128,T191
DataWait->Error	99	Covered	T53,T112,T192
Disabled->EndPointClear	63	Covered	T1,T3,T6
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T4,T12,T64
EndPointClear->Error	99	Covered	T16,T19,T20
EndPointClear->Idle	68	Covered	T1,T3,T6
Idle->DataWait	75	Covered	T10,T45,T47
Idle->Disabled	107	Covered	T1,T4,T26
Idle->Error	99	Covered	T17,T36,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T6
Idle	-	1	1	-	Covered	T10,T45,T47
Idle	-	1	0	-	Covered	T10,T45,T36
Idle	-	0	-	-	Covered	T1,T3,T6
DataWait	-	-	-	1	Covered	T10,T45,T47
DataWait	-	-	-	0	Covered	T10,T45,T47
AckPls	-	-	-	-	Covered	T10,T45,T47
Error	-	-	-	-	Covered	T16,T17,T36
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T17,T36
0	1	Covered	T26,T11,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221079372	154106	0	0
FpvSecCmErrorStEscalate_A	221079372	155149	0	0
u_state_regs_A	221079372	220911394	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	154106	0	0
T7	0	1110	0	0
T8	0	194	0	0
T9	0	662	0	0
T16	46398	18152	0	0
T17	1907	1102	0	0
T18	0	661	0	0
T21	4559	0	0	0
T36	1056	600	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	352	0	0
T56	0	362	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	390	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	155149	0	0
T7	0	1111	0	0
T8	0	195	0	0
T9	0	663	0	0
T16	46398	18412	0	0
T17	1907	1103	0	0
T18	0	662	0	0
T21	4559	0	0	0
T36	1056	601	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	353	0	0
T56	0	363	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	391	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T11,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T46,T45,T47
DataWait	75	Covered	T46,T45,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T6
Error	99	Covered	T16,T17,T36
Idle	68	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T177
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T46,T45,T47
DataWait->AckPls	80	Covered	T46,T45,T47
DataWait->Disabled	107	Covered	T99,T193,T194
DataWait->Error	99	Covered	T18
Disabled->EndPointClear	63	Covered	T1,T3,T6
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T4,T12,T64
EndPointClear->Error	99	Covered	T16,T19,T20
EndPointClear->Idle	68	Covered	T1,T3,T6
Idle->DataWait	75	Covered	T46,T45,T47
Idle->Disabled	107	Covered	T1,T4,T26
Idle->Error	99	Covered	T17,T36,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T6
Idle	-	1	1	-	Covered	T46,T45,T47
Idle	-	1	0	-	Covered	T46,T45,T47
Idle	-	0	-	-	Covered	T1,T3,T6
DataWait	-	-	-	1	Covered	T46,T45,T47
DataWait	-	-	-	0	Covered	T46,T45,T47
AckPls	-	-	-	-	Covered	T46,T45,T47
Error	-	-	-	-	Covered	T16,T17,T36
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T17,T36
0	1	Covered	T26,T11,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221079372	154106	0	0
FpvSecCmErrorStEscalate_A	221079372	155149	0	0
u_state_regs_A	221079372	220911394	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	154106	0	0
T7	0	1110	0	0
T8	0	194	0	0
T9	0	662	0	0
T16	46398	18152	0	0
T17	1907	1102	0	0
T18	0	661	0	0
T21	4559	0	0	0
T36	1056	600	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	352	0	0
T56	0	362	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	390	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	155149	0	0
T7	0	1111	0	0
T8	0	195	0	0
T9	0	663	0	0
T16	46398	18412	0	0
T17	1907	1103	0	0
T18	0	662	0	0
T21	4559	0	0	0
T36	1056	601	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	353	0	0
T56	0	363	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T174	0	391	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0