Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T39
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T40,T41
1	0	1	Covered	T10,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441467024	1006235	0	0
DepthKnown_A	442158744	441822788	0	0
RvalidKnown_A	442158744	441822788	0	0
WreadyKnown_A	442158744	441822788	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	441833730	1100502	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441467024	1006235	0	0
T7	0	81	0	0
T10	9764	3233	0	0
T11	4886	600	0	0
T12	6238	3306	0	0
T16	1396	0	0	0
T17	302	0	0	0
T21	0	5181	0	0
T22	0	5520	0	0
T32	0	785	0	0
T36	176	0	0	0
T45	8392	0	0	0
T46	4580	0	0	0
T60	2988	0	0	0
T64	42084	0	0	0
T71	0	1885	0	0
T73	0	3352	0	0
T75	0	10186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442158744	441822788	0	0
T1	1043202	1043174	0	0
T2	3318	3182	0	0
T3	4418	4228	0	0
T4	10526	9986	0	0
T6	2546	2420	0	0
T23	7400	7232	0	0
T24	7474	7332	0	0
T25	1782	1660	0	0
T26	1374	1268	0	0
T27	7986	7822	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442158744	441822788	0	0
T1	1043202	1043174	0	0
T2	3318	3182	0	0
T3	4418	4228	0	0
T4	10526	9986	0	0
T6	2546	2420	0	0
T23	7400	7232	0	0
T24	7474	7332	0	0
T25	1782	1660	0	0
T26	1374	1268	0	0
T27	7986	7822	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442158744	441822788	0	0
T1	1043202	1043174	0	0
T2	3318	3182	0	0
T3	4418	4228	0	0
T4	10526	9986	0	0
T6	2546	2420	0	0
T23	7400	7232	0	0
T24	7474	7332	0	0
T25	1782	1660	0	0
T26	1374	1268	0	0
T27	7986	7822	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	441833730	1100502	0	0
T7	0	3402	0	0
T10	9764	3233	0	0
T11	4886	600	0	0
T12	6238	3306	0	0
T16	1396	0	0	0
T17	3814	238	0	0
T18	0	281	0	0
T21	0	5181	0	0
T22	0	5520	0	0
T36	2112	222	0	0
T45	8392	0	0	0
T46	4580	0	0	0
T60	2988	0	0	0
T64	42084	0	0	0
T75	0	10186	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T16,T76
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T77
1	0	1	Covered	T10,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220733512	498293	0	0
DepthKnown_A	221079372	220911394	0	0
RvalidKnown_A	221079372	220911394	0	0
WreadyKnown_A	221079372	220911394	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	220916865	545177	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220733512	498293	0	0
T7	0	35	0	0
T10	4882	1558	0	0
T11	2443	301	0	0
T12	3119	1610	0	0
T16	698	0	0	0
T17	151	0	0	0
T21	0	2576	0	0
T22	0	2752	0	0
T32	0	382	0	0
T36	88	0	0	0
T45	4196	0	0	0
T46	2290	0	0	0
T60	1494	0	0	0
T64	21042	0	0	0
T71	0	929	0	0
T73	0	1584	0	0
T75	0	5043	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	220916865	545177	0	0
T7	0	1687	0	0
T10	4882	1558	0	0
T11	2443	301	0	0
T12	3119	1610	0	0
T16	698	0	0	0
T17	1907	120	0	0
T18	0	143	0	0
T21	0	2576	0	0
T22	0	2752	0	0
T36	1056	112	0	0
T45	4196	0	0	0
T46	2290	0	0	0
T60	1494	0	0	0
T64	21042	0	0	0
T75	0	5043	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T39
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T40,T41,T78
1	0	1	Covered	T10,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220733512	507942	0	0
DepthKnown_A	221079372	220911394	0	0
RvalidKnown_A	221079372	220911394	0	0
WreadyKnown_A	221079372	220911394	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	220916865	555325	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220733512	507942	0	0
T7	0	46	0	0
T10	4882	1675	0	0
T11	2443	299	0	0
T12	3119	1696	0	0
T16	698	0	0	0
T17	151	0	0	0
T21	0	2605	0	0
T22	0	2768	0	0
T32	0	403	0	0
T36	88	0	0	0
T45	4196	0	0	0
T46	2290	0	0	0
T60	1494	0	0	0
T64	21042	0	0	0
T71	0	956	0	0
T73	0	1768	0	0
T75	0	5143	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	220916865	555325	0	0
T7	0	1715	0	0
T10	4882	1675	0	0
T11	2443	299	0	0
T12	3119	1696	0	0
T16	698	0	0	0
T17	1907	118	0	0
T18	0	138	0	0
T21	0	2605	0	0
T22	0	2768	0	0
T36	1056	110	0	0
T45	4196	0	0	0
T46	2290	0	0	0
T60	1494	0	0	0
T64	21042	0	0	0
T75	0	5143	0	0