Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 7333 1 T54 4 T55 47 T56 26
all_values[1] 7333 1 T54 4 T55 47 T56 26


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7489 1 T54 5 T55 51 T56 29
auto[1] 7177 1 T54 3 T55 43 T56 23


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5791 1 T54 5 T55 36 T56 27
auto[1] 8875 1 T54 3 T55 58 T56 25


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8652 1 T54 7 T55 53 T56 34
auto[1] 6014 1 T54 1 T55 41 T56 18


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 1488 1 T54 3 T55 10 T56 13
all_values[0] auto[0] auto[0] auto[1] 691 1 T55 6 T56 4 T35 7
all_values[0] auto[0] auto[1] auto[0] 1397 1 T54 1 T55 6 T56 1
all_values[0] auto[0] auto[1] auto[1] 757 1 T55 4 T56 1 T35 2
all_values[0] auto[1] auto[0] auto[1] 1563 1 T55 13 T56 5 T35 11
all_values[0] auto[1] auto[1] auto[1] 1437 1 T55 8 T56 2 T35 17
all_values[1] auto[0] auto[0] auto[0] 1508 1 T54 1 T55 6 T56 3
all_values[1] auto[0] auto[0] auto[1] 699 1 T54 1 T55 3 T35 5
all_values[1] auto[0] auto[1] auto[0] 1398 1 T55 14 T56 10 T35 14
all_values[1] auto[0] auto[1] auto[1] 714 1 T54 1 T55 4 T56 2
all_values[1] auto[1] auto[0] auto[1] 1540 1 T55 13 T56 4 T35 17
all_values[1] auto[1] auto[1] auto[1] 1474 1 T54 1 T55 7 T56 7


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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