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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.47 98.24 93.78 97.02 91.86 96.33 99.77 91.31


Total test records in report: 977
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T64 /workspace/coverage/default/3.edn_sec_cm.2200312972 Jun 07 08:32:39 PM PDT 24 Jun 07 08:32:59 PM PDT 24 661784902 ps
T803 /workspace/coverage/default/15.edn_alert.2627406287 Jun 07 08:33:16 PM PDT 24 Jun 07 08:33:20 PM PDT 24 71389099 ps
T804 /workspace/coverage/default/30.edn_disable_auto_req_mode.1865862192 Jun 07 08:33:21 PM PDT 24 Jun 07 08:33:30 PM PDT 24 23232030 ps
T167 /workspace/coverage/default/33.edn_alert.2250904456 Jun 07 08:33:32 PM PDT 24 Jun 07 08:33:43 PM PDT 24 74049564 ps
T805 /workspace/coverage/default/243.edn_genbits.4200727175 Jun 07 08:34:16 PM PDT 24 Jun 07 08:34:26 PM PDT 24 58762389 ps
T806 /workspace/coverage/default/20.edn_disable_auto_req_mode.210541184 Jun 07 08:33:15 PM PDT 24 Jun 07 08:33:19 PM PDT 24 44185714 ps
T807 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1036406805 Jun 07 08:33:25 PM PDT 24 Jun 07 08:35:10 PM PDT 24 8366549599 ps
T808 /workspace/coverage/default/33.edn_genbits.4039030849 Jun 07 08:33:54 PM PDT 24 Jun 07 08:33:59 PM PDT 24 88932120 ps
T809 /workspace/coverage/default/72.edn_err.2406912349 Jun 07 08:33:54 PM PDT 24 Jun 07 08:34:00 PM PDT 24 73272272 ps
T810 /workspace/coverage/default/18.edn_genbits.305925963 Jun 07 08:33:07 PM PDT 24 Jun 07 08:33:11 PM PDT 24 143321219 ps
T811 /workspace/coverage/default/33.edn_intr.3757390278 Jun 07 08:33:20 PM PDT 24 Jun 07 08:33:27 PM PDT 24 24697574 ps
T812 /workspace/coverage/default/27.edn_disable.1681477622 Jun 07 08:33:23 PM PDT 24 Jun 07 08:33:34 PM PDT 24 11239938 ps
T188 /workspace/coverage/default/38.edn_disable.2295866205 Jun 07 08:33:27 PM PDT 24 Jun 07 08:33:38 PM PDT 24 37231321 ps
T813 /workspace/coverage/default/56.edn_genbits.1119051150 Jun 07 08:33:57 PM PDT 24 Jun 07 08:34:03 PM PDT 24 38549842 ps
T814 /workspace/coverage/default/49.edn_disable.486552367 Jun 07 08:33:41 PM PDT 24 Jun 07 08:33:45 PM PDT 24 82860880 ps
T815 /workspace/coverage/default/15.edn_disable.408519382 Jun 07 08:33:03 PM PDT 24 Jun 07 08:33:07 PM PDT 24 23493013 ps
T816 /workspace/coverage/default/181.edn_genbits.3953971466 Jun 07 08:34:15 PM PDT 24 Jun 07 08:34:25 PM PDT 24 171074333 ps
T817 /workspace/coverage/default/11.edn_err.1446924356 Jun 07 08:32:57 PM PDT 24 Jun 07 08:33:02 PM PDT 24 59517731 ps
T818 /workspace/coverage/default/241.edn_genbits.3649949946 Jun 07 08:34:18 PM PDT 24 Jun 07 08:34:29 PM PDT 24 32593693 ps
T819 /workspace/coverage/default/22.edn_err.2454579238 Jun 07 08:33:18 PM PDT 24 Jun 07 08:33:25 PM PDT 24 46743931 ps
T820 /workspace/coverage/default/40.edn_disable.897774397 Jun 07 08:33:27 PM PDT 24 Jun 07 08:33:40 PM PDT 24 99744072 ps
T821 /workspace/coverage/default/33.edn_disable.2327104993 Jun 07 08:33:23 PM PDT 24 Jun 07 08:33:33 PM PDT 24 23850918 ps
T822 /workspace/coverage/default/159.edn_genbits.4104615962 Jun 07 08:34:10 PM PDT 24 Jun 07 08:34:17 PM PDT 24 52108285 ps
T116 /workspace/coverage/default/30.edn_alert.3877910877 Jun 07 08:33:20 PM PDT 24 Jun 07 08:33:29 PM PDT 24 40419063 ps
T162 /workspace/coverage/default/33.edn_err.2208843632 Jun 07 08:33:22 PM PDT 24 Jun 07 08:33:32 PM PDT 24 23520924 ps
T224 /workspace/coverage/default/32.edn_stress_all.2010342414 Jun 07 08:33:24 PM PDT 24 Jun 07 08:33:35 PM PDT 24 49192123 ps
T65 /workspace/coverage/default/4.edn_sec_cm.2203966590 Jun 07 08:32:35 PM PDT 24 Jun 07 08:32:53 PM PDT 24 460535418 ps
T128 /workspace/coverage/default/48.edn_alert.183481982 Jun 07 08:33:41 PM PDT 24 Jun 07 08:33:45 PM PDT 24 53559665 ps
T225 /workspace/coverage/default/46.edn_err.1560730384 Jun 07 08:33:41 PM PDT 24 Jun 07 08:33:45 PM PDT 24 38613919 ps
T226 /workspace/coverage/default/43.edn_alert_test.144945126 Jun 07 08:33:24 PM PDT 24 Jun 07 08:33:34 PM PDT 24 19410959 ps
T227 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.4293637191 Jun 07 08:33:25 PM PDT 24 Jun 07 08:38:54 PM PDT 24 14347661969 ps
T228 /workspace/coverage/default/287.edn_genbits.4282408051 Jun 07 08:34:33 PM PDT 24 Jun 07 08:34:43 PM PDT 24 152837075 ps
T229 /workspace/coverage/default/10.edn_genbits.792266196 Jun 07 08:32:58 PM PDT 24 Jun 07 08:33:04 PM PDT 24 59258978 ps
T823 /workspace/coverage/default/30.edn_smoke.1509157996 Jun 07 08:33:25 PM PDT 24 Jun 07 08:33:35 PM PDT 24 29882933 ps
T824 /workspace/coverage/default/171.edn_genbits.776644539 Jun 07 08:34:16 PM PDT 24 Jun 07 08:34:26 PM PDT 24 86426557 ps
T825 /workspace/coverage/default/36.edn_disable.1127475988 Jun 07 08:33:22 PM PDT 24 Jun 07 08:33:36 PM PDT 24 10693370 ps
T826 /workspace/coverage/default/34.edn_intr.1143665361 Jun 07 08:33:42 PM PDT 24 Jun 07 08:33:46 PM PDT 24 37136132 ps
T827 /workspace/coverage/default/158.edn_genbits.1347206646 Jun 07 08:34:12 PM PDT 24 Jun 07 08:34:21 PM PDT 24 199434043 ps
T828 /workspace/coverage/default/26.edn_disable_auto_req_mode.307157613 Jun 07 08:33:24 PM PDT 24 Jun 07 08:33:34 PM PDT 24 70376817 ps
T829 /workspace/coverage/default/28.edn_stress_all.2504037491 Jun 07 08:33:27 PM PDT 24 Jun 07 08:33:41 PM PDT 24 406109663 ps
T830 /workspace/coverage/default/165.edn_genbits.2381824143 Jun 07 08:34:08 PM PDT 24 Jun 07 08:34:17 PM PDT 24 282098054 ps
T831 /workspace/coverage/default/270.edn_genbits.4213727281 Jun 07 08:34:27 PM PDT 24 Jun 07 08:34:40 PM PDT 24 61692881 ps
T832 /workspace/coverage/default/29.edn_stress_all.39305836 Jun 07 08:33:18 PM PDT 24 Jun 07 08:33:26 PM PDT 24 360433025 ps
T833 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2147868342 Jun 07 08:33:31 PM PDT 24 Jun 07 08:39:05 PM PDT 24 37480794718 ps
T834 /workspace/coverage/default/21.edn_smoke.418396757 Jun 07 08:33:13 PM PDT 24 Jun 07 08:33:17 PM PDT 24 53863414 ps
T835 /workspace/coverage/default/47.edn_stress_all.3083494666 Jun 07 08:33:53 PM PDT 24 Jun 07 08:33:59 PM PDT 24 921015687 ps
T836 /workspace/coverage/default/122.edn_genbits.1068776858 Jun 07 08:34:05 PM PDT 24 Jun 07 08:34:12 PM PDT 24 136320646 ps
T837 /workspace/coverage/default/185.edn_genbits.3765701789 Jun 07 08:34:18 PM PDT 24 Jun 07 08:34:29 PM PDT 24 39305415 ps
T275 /workspace/coverage/default/44.edn_alert.891846500 Jun 07 08:33:57 PM PDT 24 Jun 07 08:34:03 PM PDT 24 39783156 ps
T838 /workspace/coverage/default/36.edn_err.3456944626 Jun 07 08:34:01 PM PDT 24 Jun 07 08:34:08 PM PDT 24 53350503 ps
T839 /workspace/coverage/default/119.edn_genbits.3916442771 Jun 07 08:34:09 PM PDT 24 Jun 07 08:34:16 PM PDT 24 77140633 ps
T840 /workspace/coverage/default/17.edn_smoke.4217385083 Jun 07 08:33:16 PM PDT 24 Jun 07 08:33:21 PM PDT 24 15831733 ps
T841 /workspace/coverage/default/64.edn_err.2146163049 Jun 07 08:33:59 PM PDT 24 Jun 07 08:34:07 PM PDT 24 25420133 ps
T842 /workspace/coverage/default/42.edn_genbits.3561925845 Jun 07 08:34:02 PM PDT 24 Jun 07 08:34:09 PM PDT 24 54429132 ps
T843 /workspace/coverage/default/236.edn_genbits.344681316 Jun 07 08:34:15 PM PDT 24 Jun 07 08:34:25 PM PDT 24 87305519 ps
T844 /workspace/coverage/default/41.edn_disable.825415354 Jun 07 08:34:02 PM PDT 24 Jun 07 08:34:09 PM PDT 24 115157555 ps
T117 /workspace/coverage/default/41.edn_alert.955011659 Jun 07 08:33:27 PM PDT 24 Jun 07 08:33:38 PM PDT 24 127592716 ps
T845 /workspace/coverage/default/24.edn_alert_test.2745964228 Jun 07 08:33:20 PM PDT 24 Jun 07 08:33:28 PM PDT 24 57047033 ps
T846 /workspace/coverage/default/225.edn_genbits.1453188828 Jun 07 08:34:16 PM PDT 24 Jun 07 08:34:27 PM PDT 24 56339742 ps
T847 /workspace/coverage/default/78.edn_genbits.2728307555 Jun 07 08:33:55 PM PDT 24 Jun 07 08:34:01 PM PDT 24 58162116 ps
T848 /workspace/coverage/default/3.edn_smoke.3606603519 Jun 07 08:32:35 PM PDT 24 Jun 07 08:32:47 PM PDT 24 60878427 ps
T849 /workspace/coverage/default/46.edn_smoke.834779133 Jun 07 08:33:54 PM PDT 24 Jun 07 08:34:00 PM PDT 24 18470286 ps
T230 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4182439976 Jun 07 08:11:36 PM PDT 24 Jun 07 08:11:40 PM PDT 24 57976520 ps
T850 /workspace/coverage/cover_reg_top/1.edn_intr_test.3320057673 Jun 07 08:11:35 PM PDT 24 Jun 07 08:11:37 PM PDT 24 38215935 ps
T851 /workspace/coverage/cover_reg_top/15.edn_tl_errors.964823543 Jun 07 08:11:59 PM PDT 24 Jun 07 08:12:06 PM PDT 24 229115521 ps
T231 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4026451393 Jun 07 08:11:49 PM PDT 24 Jun 07 08:11:53 PM PDT 24 115909996 ps
T232 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3925910725 Jun 07 08:11:48 PM PDT 24 Jun 07 08:11:54 PM PDT 24 87391431 ps
T251 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1197187948 Jun 07 08:11:53 PM PDT 24 Jun 07 08:11:59 PM PDT 24 74574574 ps
T852 /workspace/coverage/cover_reg_top/4.edn_tl_errors.360248386 Jun 07 08:11:47 PM PDT 24 Jun 07 08:11:53 PM PDT 24 291478045 ps
T853 /workspace/coverage/cover_reg_top/11.edn_intr_test.1375300930 Jun 07 08:11:53 PM PDT 24 Jun 07 08:11:59 PM PDT 24 23879983 ps
T854 /workspace/coverage/cover_reg_top/6.edn_intr_test.3849281910 Jun 07 08:11:53 PM PDT 24 Jun 07 08:11:59 PM PDT 24 39994723 ps
T855 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1625044673 Jun 07 08:11:57 PM PDT 24 Jun 07 08:12:06 PM PDT 24 114393920 ps
T856 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2740681375 Jun 07 08:11:52 PM PDT 24 Jun 07 08:11:59 PM PDT 24 50416937 ps
T252 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1950764441 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:56 PM PDT 24 15222868 ps
T857 /workspace/coverage/cover_reg_top/42.edn_intr_test.1568189594 Jun 07 08:12:09 PM PDT 24 Jun 07 08:12:15 PM PDT 24 11439654 ps
T858 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1891649602 Jun 07 08:11:52 PM PDT 24 Jun 07 08:12:02 PM PDT 24 644398398 ps
T262 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1268608031 Jun 07 08:11:56 PM PDT 24 Jun 07 08:12:03 PM PDT 24 173025001 ps
T233 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4190484745 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:11 PM PDT 24 39200531 ps
T263 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2992190137 Jun 07 08:11:55 PM PDT 24 Jun 07 08:12:02 PM PDT 24 337932743 ps
T859 /workspace/coverage/cover_reg_top/12.edn_intr_test.622432946 Jun 07 08:11:49 PM PDT 24 Jun 07 08:11:54 PM PDT 24 14441896 ps
T261 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1327031533 Jun 07 08:11:35 PM PDT 24 Jun 07 08:11:38 PM PDT 24 11852276 ps
T860 /workspace/coverage/cover_reg_top/39.edn_intr_test.3579554677 Jun 07 08:12:07 PM PDT 24 Jun 07 08:12:12 PM PDT 24 49959983 ps
T861 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2814586250 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:55 PM PDT 24 16785957 ps
T862 /workspace/coverage/cover_reg_top/7.edn_intr_test.2944364909 Jun 07 08:11:49 PM PDT 24 Jun 07 08:11:53 PM PDT 24 33981343 ps
T863 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4101790474 Jun 07 08:11:52 PM PDT 24 Jun 07 08:12:00 PM PDT 24 253998896 ps
T864 /workspace/coverage/cover_reg_top/38.edn_intr_test.3925122907 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:12 PM PDT 24 179506702 ps
T865 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3211745090 Jun 07 08:11:59 PM PDT 24 Jun 07 08:12:05 PM PDT 24 46656069 ps
T234 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3136339711 Jun 07 08:11:49 PM PDT 24 Jun 07 08:11:54 PM PDT 24 23738233 ps
T866 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1534709403 Jun 07 08:11:49 PM PDT 24 Jun 07 08:11:56 PM PDT 24 130072423 ps
T867 /workspace/coverage/cover_reg_top/43.edn_intr_test.2123475148 Jun 07 08:12:07 PM PDT 24 Jun 07 08:12:13 PM PDT 24 29513737 ps
T264 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.588177639 Jun 07 08:12:02 PM PDT 24 Jun 07 08:12:07 PM PDT 24 175618625 ps
T253 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4255751947 Jun 07 08:11:48 PM PDT 24 Jun 07 08:11:53 PM PDT 24 104329873 ps
T868 /workspace/coverage/cover_reg_top/22.edn_intr_test.1639404245 Jun 07 08:12:10 PM PDT 24 Jun 07 08:12:16 PM PDT 24 12257625 ps
T869 /workspace/coverage/cover_reg_top/0.edn_intr_test.1461561239 Jun 07 08:11:35 PM PDT 24 Jun 07 08:11:37 PM PDT 24 15029825 ps
T235 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1782760438 Jun 07 08:11:37 PM PDT 24 Jun 07 08:11:40 PM PDT 24 143432873 ps
T254 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.555517939 Jun 07 08:11:48 PM PDT 24 Jun 07 08:11:53 PM PDT 24 48856664 ps
T870 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3093021286 Jun 07 08:11:36 PM PDT 24 Jun 07 08:11:39 PM PDT 24 38086784 ps
T871 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1641279315 Jun 07 08:12:07 PM PDT 24 Jun 07 08:12:13 PM PDT 24 43089729 ps
T872 /workspace/coverage/cover_reg_top/15.edn_intr_test.2118992172 Jun 07 08:11:59 PM PDT 24 Jun 07 08:12:04 PM PDT 24 40250485 ps
T873 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3322986430 Jun 07 08:11:51 PM PDT 24 Jun 07 08:11:57 PM PDT 24 180655312 ps
T874 /workspace/coverage/cover_reg_top/12.edn_csr_rw.586784367 Jun 07 08:11:55 PM PDT 24 Jun 07 08:12:01 PM PDT 24 39468198 ps
T875 /workspace/coverage/cover_reg_top/8.edn_intr_test.1585390568 Jun 07 08:11:54 PM PDT 24 Jun 07 08:12:00 PM PDT 24 39423104 ps
T236 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2734381017 Jun 07 08:11:47 PM PDT 24 Jun 07 08:11:52 PM PDT 24 33019760 ps
T876 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4115229102 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:56 PM PDT 24 31572706 ps
T877 /workspace/coverage/cover_reg_top/30.edn_intr_test.3907756231 Jun 07 08:12:07 PM PDT 24 Jun 07 08:12:13 PM PDT 24 17936607 ps
T878 /workspace/coverage/cover_reg_top/10.edn_intr_test.1814024275 Jun 07 08:11:51 PM PDT 24 Jun 07 08:11:56 PM PDT 24 29532035 ps
T879 /workspace/coverage/cover_reg_top/2.edn_intr_test.1838774245 Jun 07 08:11:37 PM PDT 24 Jun 07 08:11:40 PM PDT 24 54056070 ps
T880 /workspace/coverage/cover_reg_top/45.edn_intr_test.4009107607 Jun 07 08:12:03 PM PDT 24 Jun 07 08:12:08 PM PDT 24 16221527 ps
T237 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2139192718 Jun 07 08:11:39 PM PDT 24 Jun 07 08:11:45 PM PDT 24 31226286 ps
T255 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1194042068 Jun 07 08:11:59 PM PDT 24 Jun 07 08:12:05 PM PDT 24 87346982 ps
T256 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.876457656 Jun 07 08:11:49 PM PDT 24 Jun 07 08:11:55 PM PDT 24 69157919 ps
T881 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2060871634 Jun 07 08:11:52 PM PDT 24 Jun 07 08:12:00 PM PDT 24 176826543 ps
T882 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1603488135 Jun 07 08:11:58 PM PDT 24 Jun 07 08:12:04 PM PDT 24 53800632 ps
T883 /workspace/coverage/cover_reg_top/9.edn_intr_test.3156473086 Jun 07 08:11:53 PM PDT 24 Jun 07 08:11:59 PM PDT 24 89899346 ps
T884 /workspace/coverage/cover_reg_top/3.edn_intr_test.2180809609 Jun 07 08:11:45 PM PDT 24 Jun 07 08:11:50 PM PDT 24 14279329 ps
T885 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1487637774 Jun 07 08:11:35 PM PDT 24 Jun 07 08:11:38 PM PDT 24 23455480 ps
T266 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3690647778 Jun 07 08:11:51 PM PDT 24 Jun 07 08:11:58 PM PDT 24 130332314 ps
T886 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1634399458 Jun 07 08:12:02 PM PDT 24 Jun 07 08:12:08 PM PDT 24 55137298 ps
T887 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1630686303 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:13 PM PDT 24 319717734 ps
T888 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3715791670 Jun 07 08:11:52 PM PDT 24 Jun 07 08:12:00 PM PDT 24 141858479 ps
T889 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.589008709 Jun 07 08:11:53 PM PDT 24 Jun 07 08:12:00 PM PDT 24 79273875 ps
T890 /workspace/coverage/cover_reg_top/13.edn_intr_test.385368490 Jun 07 08:11:57 PM PDT 24 Jun 07 08:12:03 PM PDT 24 56983651 ps
T238 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3424792162 Jun 07 08:11:59 PM PDT 24 Jun 07 08:12:05 PM PDT 24 129933812 ps
T891 /workspace/coverage/cover_reg_top/48.edn_intr_test.835818811 Jun 07 08:12:07 PM PDT 24 Jun 07 08:12:12 PM PDT 24 37750810 ps
T892 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3891089892 Jun 07 08:11:56 PM PDT 24 Jun 07 08:12:03 PM PDT 24 83256338 ps
T269 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.895337586 Jun 07 08:12:00 PM PDT 24 Jun 07 08:12:07 PM PDT 24 326247518 ps
T893 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.96774226 Jun 07 08:11:58 PM PDT 24 Jun 07 08:12:05 PM PDT 24 139064912 ps
T894 /workspace/coverage/cover_reg_top/24.edn_intr_test.3377852703 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:11 PM PDT 24 25088730 ps
T895 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.22044456 Jun 07 08:12:02 PM PDT 24 Jun 07 08:12:07 PM PDT 24 44837765 ps
T896 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2168451708 Jun 07 08:11:52 PM PDT 24 Jun 07 08:11:58 PM PDT 24 43267118 ps
T897 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2726395588 Jun 07 08:11:59 PM PDT 24 Jun 07 08:12:06 PM PDT 24 132146941 ps
T898 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.80595377 Jun 07 08:12:00 PM PDT 24 Jun 07 08:12:06 PM PDT 24 272741319 ps
T899 /workspace/coverage/cover_reg_top/41.edn_intr_test.1230921020 Jun 07 08:12:09 PM PDT 24 Jun 07 08:12:15 PM PDT 24 39176948 ps
T900 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3697307639 Jun 07 08:11:37 PM PDT 24 Jun 07 08:11:41 PM PDT 24 62509375 ps
T901 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2467884686 Jun 07 08:11:46 PM PDT 24 Jun 07 08:11:53 PM PDT 24 368599239 ps
T902 /workspace/coverage/cover_reg_top/21.edn_intr_test.2016470106 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:11 PM PDT 24 116022408 ps
T239 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1680187701 Jun 07 08:11:45 PM PDT 24 Jun 07 08:11:50 PM PDT 24 16800377 ps
T903 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3948084040 Jun 07 08:11:59 PM PDT 24 Jun 07 08:12:07 PM PDT 24 108891934 ps
T904 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3925638637 Jun 07 08:12:04 PM PDT 24 Jun 07 08:12:10 PM PDT 24 131443102 ps
T905 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2728731356 Jun 07 08:11:39 PM PDT 24 Jun 07 08:11:44 PM PDT 24 47031900 ps
T906 /workspace/coverage/cover_reg_top/23.edn_intr_test.3259109149 Jun 07 08:12:04 PM PDT 24 Jun 07 08:12:10 PM PDT 24 39726943 ps
T907 /workspace/coverage/cover_reg_top/28.edn_intr_test.2574820853 Jun 07 08:12:09 PM PDT 24 Jun 07 08:12:14 PM PDT 24 14789604 ps
T908 /workspace/coverage/cover_reg_top/35.edn_intr_test.90994375 Jun 07 08:12:04 PM PDT 24 Jun 07 08:12:09 PM PDT 24 78305220 ps
T240 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2207131345 Jun 07 08:11:48 PM PDT 24 Jun 07 08:11:53 PM PDT 24 15842407 ps
T909 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4046695174 Jun 07 08:12:04 PM PDT 24 Jun 07 08:12:10 PM PDT 24 66098928 ps
T910 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.293765427 Jun 07 08:11:54 PM PDT 24 Jun 07 08:12:01 PM PDT 24 50301971 ps
T241 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1691475541 Jun 07 08:11:33 PM PDT 24 Jun 07 08:11:36 PM PDT 24 34029607 ps
T242 /workspace/coverage/cover_reg_top/9.edn_csr_rw.589185383 Jun 07 08:11:53 PM PDT 24 Jun 07 08:11:59 PM PDT 24 36422618 ps
T911 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1812588519 Jun 07 08:11:58 PM PDT 24 Jun 07 08:12:04 PM PDT 24 32889599 ps
T912 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1216180042 Jun 07 08:11:55 PM PDT 24 Jun 07 08:12:02 PM PDT 24 19877966 ps
T913 /workspace/coverage/cover_reg_top/27.edn_intr_test.340105841 Jun 07 08:12:07 PM PDT 24 Jun 07 08:12:12 PM PDT 24 13743070 ps
T914 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4289029953 Jun 07 08:11:36 PM PDT 24 Jun 07 08:11:40 PM PDT 24 45991429 ps
T915 /workspace/coverage/cover_reg_top/17.edn_intr_test.1297194923 Jun 07 08:12:00 PM PDT 24 Jun 07 08:12:05 PM PDT 24 34963856 ps
T916 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1752636635 Jun 07 08:11:55 PM PDT 24 Jun 07 08:12:01 PM PDT 24 22261016 ps
T917 /workspace/coverage/cover_reg_top/34.edn_intr_test.242968671 Jun 07 08:12:09 PM PDT 24 Jun 07 08:12:15 PM PDT 24 12782253 ps
T918 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1000713556 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:56 PM PDT 24 51659480 ps
T919 /workspace/coverage/cover_reg_top/33.edn_intr_test.2045456467 Jun 07 08:12:03 PM PDT 24 Jun 07 08:12:09 PM PDT 24 165328267 ps
T920 /workspace/coverage/cover_reg_top/18.edn_intr_test.4068316192 Jun 07 08:12:03 PM PDT 24 Jun 07 08:12:08 PM PDT 24 33874929 ps
T921 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2289901694 Jun 07 08:12:01 PM PDT 24 Jun 07 08:12:07 PM PDT 24 40038469 ps
T922 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1673468088 Jun 07 08:12:02 PM PDT 24 Jun 07 08:12:07 PM PDT 24 35352644 ps
T923 /workspace/coverage/cover_reg_top/13.edn_csr_rw.697775626 Jun 07 08:11:58 PM PDT 24 Jun 07 08:12:04 PM PDT 24 12225865 ps
T924 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1035024721 Jun 07 08:11:47 PM PDT 24 Jun 07 08:11:52 PM PDT 24 175522684 ps
T925 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1639862227 Jun 07 08:11:46 PM PDT 24 Jun 07 08:11:57 PM PDT 24 1306571399 ps
T267 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2295874713 Jun 07 08:11:48 PM PDT 24 Jun 07 08:11:54 PM PDT 24 44086437 ps
T926 /workspace/coverage/cover_reg_top/37.edn_intr_test.899276250 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:11 PM PDT 24 50863392 ps
T927 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2557511052 Jun 07 08:11:47 PM PDT 24 Jun 07 08:11:52 PM PDT 24 20186544 ps
T928 /workspace/coverage/cover_reg_top/5.edn_intr_test.3328205411 Jun 07 08:11:47 PM PDT 24 Jun 07 08:11:52 PM PDT 24 36697425 ps
T929 /workspace/coverage/cover_reg_top/40.edn_intr_test.1941200064 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:11 PM PDT 24 14623202 ps
T246 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2942943135 Jun 07 08:11:48 PM PDT 24 Jun 07 08:11:52 PM PDT 24 31387606 ps
T243 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.356438763 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:56 PM PDT 24 14334498 ps
T930 /workspace/coverage/cover_reg_top/19.edn_intr_test.2780449395 Jun 07 08:12:04 PM PDT 24 Jun 07 08:12:09 PM PDT 24 15563529 ps
T268 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1728908646 Jun 07 08:11:39 PM PDT 24 Jun 07 08:11:45 PM PDT 24 344673438 ps
T244 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.288977263 Jun 07 08:11:47 PM PDT 24 Jun 07 08:11:52 PM PDT 24 32172075 ps
T931 /workspace/coverage/cover_reg_top/44.edn_intr_test.2384470208 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:11 PM PDT 24 18743842 ps
T932 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4102520344 Jun 07 08:11:46 PM PDT 24 Jun 07 08:11:53 PM PDT 24 596199716 ps
T933 /workspace/coverage/cover_reg_top/6.edn_tl_errors.4002512601 Jun 07 08:11:51 PM PDT 24 Jun 07 08:11:59 PM PDT 24 140861133 ps
T934 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3336380983 Jun 07 08:12:00 PM PDT 24 Jun 07 08:12:05 PM PDT 24 38525644 ps
T935 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2577094802 Jun 07 08:12:01 PM PDT 24 Jun 07 08:12:07 PM PDT 24 57191888 ps
T936 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2656653713 Jun 07 08:11:57 PM PDT 24 Jun 07 08:12:04 PM PDT 24 77045725 ps
T937 /workspace/coverage/cover_reg_top/1.edn_tl_errors.374443969 Jun 07 08:11:39 PM PDT 24 Jun 07 08:11:47 PM PDT 24 107341385 ps
T938 /workspace/coverage/cover_reg_top/36.edn_intr_test.2414669833 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:11 PM PDT 24 108186292 ps
T939 /workspace/coverage/cover_reg_top/29.edn_intr_test.2956765354 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:12 PM PDT 24 14504052 ps
T940 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1007017544 Jun 07 08:11:49 PM PDT 24 Jun 07 08:11:54 PM PDT 24 19737449 ps
T941 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1476191530 Jun 07 08:11:35 PM PDT 24 Jun 07 08:11:38 PM PDT 24 27471927 ps
T942 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2835395422 Jun 07 08:11:51 PM PDT 24 Jun 07 08:11:58 PM PDT 24 102525501 ps
T943 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3962680983 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:55 PM PDT 24 107324034 ps
T245 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3260290368 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:56 PM PDT 24 12368906 ps
T944 /workspace/coverage/cover_reg_top/13.edn_tl_errors.14278814 Jun 07 08:11:58 PM PDT 24 Jun 07 08:12:05 PM PDT 24 43765647 ps
T247 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1418162999 Jun 07 08:11:52 PM PDT 24 Jun 07 08:11:59 PM PDT 24 39860260 ps
T945 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2928569176 Jun 07 08:12:00 PM PDT 24 Jun 07 08:12:06 PM PDT 24 83557107 ps
T946 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1532087638 Jun 07 08:11:52 PM PDT 24 Jun 07 08:12:00 PM PDT 24 463846113 ps
T947 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2166249425 Jun 07 08:11:39 PM PDT 24 Jun 07 08:11:43 PM PDT 24 48829785 ps
T948 /workspace/coverage/cover_reg_top/16.edn_intr_test.3251590508 Jun 07 08:12:00 PM PDT 24 Jun 07 08:12:05 PM PDT 24 64157392 ps
T248 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2862396654 Jun 07 08:11:59 PM PDT 24 Jun 07 08:12:05 PM PDT 24 16643468 ps
T949 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.828861096 Jun 07 08:11:36 PM PDT 24 Jun 07 08:11:42 PM PDT 24 61692755 ps
T950 /workspace/coverage/cover_reg_top/4.edn_intr_test.3971499299 Jun 07 08:11:48 PM PDT 24 Jun 07 08:11:53 PM PDT 24 49011254 ps
T270 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1529240369 Jun 07 08:11:41 PM PDT 24 Jun 07 08:11:47 PM PDT 24 451603785 ps
T951 /workspace/coverage/cover_reg_top/14.edn_intr_test.1246435791 Jun 07 08:12:01 PM PDT 24 Jun 07 08:12:06 PM PDT 24 13974992 ps
T952 /workspace/coverage/cover_reg_top/47.edn_intr_test.68251949 Jun 07 08:12:09 PM PDT 24 Jun 07 08:12:15 PM PDT 24 20542868 ps
T953 /workspace/coverage/cover_reg_top/32.edn_intr_test.927834688 Jun 07 08:12:11 PM PDT 24 Jun 07 08:12:16 PM PDT 24 140953623 ps
T954 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.964047773 Jun 07 08:11:53 PM PDT 24 Jun 07 08:11:59 PM PDT 24 15448290 ps
T271 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3016889861 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:57 PM PDT 24 723836591 ps
T955 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4239080032 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:12 PM PDT 24 17421445 ps
T249 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1335726643 Jun 07 08:11:35 PM PDT 24 Jun 07 08:11:43 PM PDT 24 503473744 ps
T956 /workspace/coverage/cover_reg_top/19.edn_tl_errors.436667464 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:13 PM PDT 24 96810485 ps
T957 /workspace/coverage/cover_reg_top/0.edn_csr_rw.108376027 Jun 07 08:11:39 PM PDT 24 Jun 07 08:11:43 PM PDT 24 217593644 ps
T958 /workspace/coverage/cover_reg_top/20.edn_intr_test.209848640 Jun 07 08:12:07 PM PDT 24 Jun 07 08:12:12 PM PDT 24 27833367 ps
T959 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3702028668 Jun 07 08:11:58 PM PDT 24 Jun 07 08:12:05 PM PDT 24 80620106 ps
T960 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1041016648 Jun 07 08:12:00 PM PDT 24 Jun 07 08:12:06 PM PDT 24 30023702 ps
T961 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.966120644 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:57 PM PDT 24 154746369 ps
T962 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3337183414 Jun 07 08:11:50 PM PDT 24 Jun 07 08:11:57 PM PDT 24 222569641 ps
T963 /workspace/coverage/cover_reg_top/46.edn_intr_test.23156614 Jun 07 08:12:06 PM PDT 24 Jun 07 08:12:11 PM PDT 24 13671218 ps
T964 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3194099204 Jun 07 08:11:52 PM PDT 24 Jun 07 08:11:58 PM PDT 24 11273647 ps
T965 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1475787800 Jun 07 08:11:45 PM PDT 24 Jun 07 08:11:52 PM PDT 24 78730199 ps
T250 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1933746339 Jun 07 08:11:56 PM PDT 24 Jun 07 08:12:02 PM PDT 24 15126760 ps
T966 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4102199672 Jun 07 08:11:53 PM PDT 24 Jun 07 08:12:00 PM PDT 24 206818818 ps
T967 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1024010435 Jun 07 08:12:01 PM PDT 24 Jun 07 08:12:08 PM PDT 24 354239722 ps
T968 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.825905593 Jun 07 08:11:53 PM PDT 24 Jun 07 08:12:01 PM PDT 24 148089896 ps
T969 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1128300019 Jun 07 08:11:47 PM PDT 24 Jun 07 08:11:55 PM PDT 24 151444272 ps
T970 /workspace/coverage/cover_reg_top/49.edn_intr_test.2999501861 Jun 07 08:12:04 PM PDT 24 Jun 07 08:12:10 PM PDT 24 28454259 ps
T971 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3262152274 Jun 07 08:12:00 PM PDT 24 Jun 07 08:12:09 PM PDT 24 110624499 ps
T972 /workspace/coverage/cover_reg_top/26.edn_intr_test.1042860257 Jun 07 08:12:12 PM PDT 24 Jun 07 08:12:17 PM PDT 24 55992809 ps
T973 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1617906990 Jun 07 08:12:00 PM PDT 24 Jun 07 08:12:07 PM PDT 24 109085071 ps
T974 /workspace/coverage/cover_reg_top/31.edn_intr_test.2751671952 Jun 07 08:12:05 PM PDT 24 Jun 07 08:12:11 PM PDT 24 21725534 ps
T975 /workspace/coverage/cover_reg_top/25.edn_intr_test.682303615 Jun 07 08:12:08 PM PDT 24 Jun 07 08:12:14 PM PDT 24 27960634 ps
T976 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.44815151 Jun 07 08:11:59 PM PDT 24 Jun 07 08:12:05 PM PDT 24 20248055 ps
T977 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3210222760 Jun 07 08:11:54 PM PDT 24 Jun 07 08:12:01 PM PDT 24 57935859 ps

Test location /workspace/coverage/default/263.edn_genbits.1301548554
Short name T1
Test name
Test status
Simulation time 148086446 ps
CPU time 2.06 seconds
Started Jun 07 08:34:27 PM PDT 24
Finished Jun 07 08:34:43 PM PDT 24
Peak memory 220024 kb
Host smart-92258b1d-357c-469a-b09c-26a858b0618a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301548554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1301548554
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3035020856
Short name T14
Test name
Test status
Simulation time 594679243 ps
CPU time 4.55 seconds
Started Jun 07 08:32:43 PM PDT 24
Finished Jun 07 08:32:56 PM PDT 24
Peak memory 235636 kb
Host smart-5ddfdbc0-7d72-4523-ba73-65ae0b133283
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035020856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3035020856
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/16.edn_alert.2669553212
Short name T26
Test name
Test status
Simulation time 25802136 ps
CPU time 1.16 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:26 PM PDT 24
Peak memory 219536 kb
Host smart-19a5758d-cf56-4e01-9e93-e89d42674fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669553212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2669553212
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2046136134
Short name T35
Test name
Test status
Simulation time 27303365069 ps
CPU time 614.17 seconds
Started Jun 07 08:33:30 PM PDT 24
Finished Jun 07 08:43:53 PM PDT 24
Peak memory 218864 kb
Host smart-507f248c-737a-4504-9b77-eebe9dba91ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046136134 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2046136134
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.edn_genbits.3084231985
Short name T41
Test name
Test status
Simulation time 57488303 ps
CPU time 1.56 seconds
Started Jun 07 08:34:07 PM PDT 24
Finished Jun 07 08:34:14 PM PDT 24
Peak memory 218516 kb
Host smart-e2a02665-5c4f-466c-97ce-2ff692617ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084231985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3084231985
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_disable.2018231003
Short name T18
Test name
Test status
Simulation time 33328120 ps
CPU time 0.83 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 216164 kb
Host smart-d3d69bee-8d5f-4a05-8c04-a25487947040
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018231003 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2018231003
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/9.edn_alert.3996291945
Short name T51
Test name
Test status
Simulation time 82624224 ps
CPU time 1.17 seconds
Started Jun 07 08:33:03 PM PDT 24
Finished Jun 07 08:33:08 PM PDT 24
Peak memory 218284 kb
Host smart-3e3719f2-add1-4ca2-8af3-7430dc12c0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996291945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3996291945
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3961590979
Short name T206
Test name
Test status
Simulation time 81174725192 ps
CPU time 1808.81 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 09:03:43 PM PDT 24
Peak memory 224880 kb
Host smart-b4bfeb82-0810-4c9f-9838-bf466e663d68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961590979 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3961590979
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3009606998
Short name T49
Test name
Test status
Simulation time 92891419 ps
CPU time 1.21 seconds
Started Jun 07 08:33:17 PM PDT 24
Finished Jun 07 08:33:22 PM PDT 24
Peak memory 216772 kb
Host smart-eceda8b9-7fe0-41f1-a782-06241ee47207
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009606998 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3009606998
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.304312964
Short name T2
Test name
Test status
Simulation time 15996519 ps
CPU time 0.95 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:35 PM PDT 24
Peak memory 216488 kb
Host smart-463f3161-3b04-4a4b-89fa-c939b3bab525
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304312964 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.304312964
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/45.edn_alert.3968165204
Short name T74
Test name
Test status
Simulation time 112426093 ps
CPU time 1.21 seconds
Started Jun 07 08:33:49 PM PDT 24
Finished Jun 07 08:33:52 PM PDT 24
Peak memory 219208 kb
Host smart-59384607-b401-49c8-948b-3903a43b84e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968165204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3968165204
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.2512661645
Short name T24
Test name
Test status
Simulation time 45212678 ps
CPU time 0.91 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:46 PM PDT 24
Peak memory 207028 kb
Host smart-34fddb5a-f780-4d10-8b90-1c20c224e1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512661645 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2512661645
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/17.edn_alert.1420876723
Short name T110
Test name
Test status
Simulation time 81452100 ps
CPU time 1.08 seconds
Started Jun 07 08:33:16 PM PDT 24
Finished Jun 07 08:33:21 PM PDT 24
Peak memory 220448 kb
Host smart-5624e541-d36d-40c3-89b6-c1b64d64058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420876723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1420876723
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3690647778
Short name T266
Test name
Test status
Simulation time 130332314 ps
CPU time 2.53 seconds
Started Jun 07 08:11:51 PM PDT 24
Finished Jun 07 08:11:58 PM PDT 24
Peak memory 206560 kb
Host smart-c28084f0-a72f-4fd4-81ae-10c880f00f08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690647778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3690647778
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/13.edn_disable.4146821313
Short name T38
Test name
Test status
Simulation time 11297496 ps
CPU time 0.84 seconds
Started Jun 07 08:33:11 PM PDT 24
Finished Jun 07 08:33:15 PM PDT 24
Peak memory 216156 kb
Host smart-106eb87d-1f38-47df-8949-313abc316ef0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146821313 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.4146821313
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4026451393
Short name T231
Test name
Test status
Simulation time 115909996 ps
CPU time 1 seconds
Started Jun 07 08:11:49 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 206424 kb
Host smart-0a5970d9-1629-4112-8b01-67549b786e2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026451393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4026451393
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/default/10.edn_alert.3093722173
Short name T151
Test name
Test status
Simulation time 82370501 ps
CPU time 1.21 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 218840 kb
Host smart-c0673e21-8379-449d-a957-b89cc949387f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093722173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3093722173
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.469677326
Short name T164
Test name
Test status
Simulation time 41959084 ps
CPU time 0.94 seconds
Started Jun 07 08:32:48 PM PDT 24
Finished Jun 07 08:32:55 PM PDT 24
Peak memory 216140 kb
Host smart-b5ba03c8-dd6b-4843-acd1-44d28d85f2fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469677326 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.469677326
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3802139076
Short name T193
Test name
Test status
Simulation time 63484649 ps
CPU time 1.25 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 216816 kb
Host smart-4c045aea-4cfa-4e05-b2e6-8c8310815faa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802139076 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3802139076
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/74.edn_err.4139242658
Short name T160
Test name
Test status
Simulation time 18227230 ps
CPU time 1.01 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 218608 kb
Host smart-b84cbe7b-a82a-452b-a1af-2bccbb94ea9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139242658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4139242658
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4248665355
Short name T99
Test name
Test status
Simulation time 91108004 ps
CPU time 1.07 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 215720 kb
Host smart-87474ce9-e647-4103-8da0-4bc5e6f217b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248665355 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4248665355
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_genbits.1533371964
Short name T9
Test name
Test status
Simulation time 58343074 ps
CPU time 1.97 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 219724 kb
Host smart-eec5768f-7c6e-4e7d-8124-6419f02fa6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533371964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1533371964
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.345675796
Short name T30
Test name
Test status
Simulation time 43703260 ps
CPU time 0.83 seconds
Started Jun 07 08:33:03 PM PDT 24
Finished Jun 07 08:33:07 PM PDT 24
Peak memory 215584 kb
Host smart-41f9e607-2310-4295-bcf7-db1063e19343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345675796 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.345675796
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/0.edn_alert.1075501810
Short name T784
Test name
Test status
Simulation time 40512355 ps
CPU time 1.2 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:46 PM PDT 24
Peak memory 218304 kb
Host smart-a6df1c71-25b4-4584-aab8-f78ffd52e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075501810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1075501810
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert.192085658
Short name T102
Test name
Test status
Simulation time 48888072 ps
CPU time 1.13 seconds
Started Jun 07 08:32:39 PM PDT 24
Finished Jun 07 08:32:51 PM PDT 24
Peak memory 219316 kb
Host smart-33aa4d69-af81-4d4f-b121-6c46a389d5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192085658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.192085658
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_err.4142362286
Short name T181
Test name
Test status
Simulation time 42121803 ps
CPU time 0.93 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:46 PM PDT 24
Peak memory 229288 kb
Host smart-0ba1deb6-b420-49b6-9845-f69a25f34477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142362286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.4142362286
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2729237131
Short name T69
Test name
Test status
Simulation time 35480317 ps
CPU time 1.29 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 216804 kb
Host smart-58aa170f-bcbc-458b-bb96-4d0d40ef344d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729237131 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2729237131
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_alert.2980831209
Short name T101
Test name
Test status
Simulation time 33650007 ps
CPU time 1.18 seconds
Started Jun 07 08:32:52 PM PDT 24
Finished Jun 07 08:32:58 PM PDT 24
Peak memory 218220 kb
Host smart-41f50001-26e3-4337-af45-a7128756ebbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980831209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2980831209
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.2809576723
Short name T115
Test name
Test status
Simulation time 71544283 ps
CPU time 1.09 seconds
Started Jun 07 08:32:56 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 218468 kb
Host smart-436224f7-5d29-4e69-8954-ceed1c5aa824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809576723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2809576723
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert.1225542724
Short name T173
Test name
Test status
Simulation time 29387432 ps
CPU time 1.14 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 220300 kb
Host smart-5b6855da-e046-4302-864e-a46a164ec1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225542724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1225542724
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/34.edn_disable.2239505438
Short name T187
Test name
Test status
Simulation time 18267967 ps
CPU time 0.89 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:33 PM PDT 24
Peak memory 216136 kb
Host smart-e94a5410-876d-4265-be6d-8a9d75d2ada2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239505438 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2239505438
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.3631582744
Short name T200
Test name
Test status
Simulation time 41637253 ps
CPU time 0.86 seconds
Started Jun 07 08:33:35 PM PDT 24
Finished Jun 07 08:33:42 PM PDT 24
Peak memory 215324 kb
Host smart-c4276543-8c9c-4038-a353-ec3fbfc544d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631582744 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3631582744
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/52.edn_genbits.1246715890
Short name T43
Test name
Test status
Simulation time 43200100 ps
CPU time 1.24 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 216988 kb
Host smart-9f11b35c-c5b0-4171-ae69-86a4551c5f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246715890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1246715890
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.427532563
Short name T88
Test name
Test status
Simulation time 36715573 ps
CPU time 0.91 seconds
Started Jun 07 08:33:02 PM PDT 24
Finished Jun 07 08:33:06 PM PDT 24
Peak memory 215640 kb
Host smart-faed9dbf-8cbf-4dab-8a0a-48eda312bd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427532563 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.427532563
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_err.2294951719
Short name T750
Test name
Test status
Simulation time 22157814 ps
CPU time 1.03 seconds
Started Jun 07 08:33:12 PM PDT 24
Finished Jun 07 08:33:15 PM PDT 24
Peak memory 224028 kb
Host smart-c97ff2ee-924d-436f-b891-69916c4cab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294951719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2294951719
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/18.edn_err.3309470353
Short name T178
Test name
Test status
Simulation time 33221329 ps
CPU time 0.88 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:24 PM PDT 24
Peak memory 218184 kb
Host smart-ffede861-2e2e-44e1-b17b-73561a00e511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309470353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3309470353
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/22.edn_alert.2500706301
Short name T109
Test name
Test status
Simulation time 23519151 ps
CPU time 1.19 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:25 PM PDT 24
Peak memory 219332 kb
Host smart-c6e07313-e9fe-4018-9d94-8d385046cf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500706301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2500706301
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert.1431341959
Short name T52
Test name
Test status
Simulation time 33696738 ps
CPU time 1.19 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:26 PM PDT 24
Peak memory 219076 kb
Host smart-9dac4617-4e7c-4a15-a548-4bad5a6b6582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431341959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1431341959
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable.2759853441
Short name T183
Test name
Test status
Simulation time 22600727 ps
CPU time 0.91 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:40 PM PDT 24
Peak memory 216304 kb
Host smart-5b16f316-6ad4-4d39-81c7-bf423c1bdf04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759853441 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2759853441
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1883537924
Short name T196
Test name
Test status
Simulation time 84147671 ps
CPU time 1.04 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:35 PM PDT 24
Peak memory 216748 kb
Host smart-e236b23a-990f-4c45-8d28-75317a743e52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883537924 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1883537924
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2596825869
Short name T185
Test name
Test status
Simulation time 36744611 ps
CPU time 1.19 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 216744 kb
Host smart-d6bcd9bf-31ec-4609-9c30-7452e749c9f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596825869 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2596825869
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.775173481
Short name T144
Test name
Test status
Simulation time 54781227 ps
CPU time 1.19 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:31 PM PDT 24
Peak memory 216856 kb
Host smart-41d692a8-dc9f-4f55-8784-1d0836992efe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775173481 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.775173481
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_alert.4163879934
Short name T134
Test name
Test status
Simulation time 24672699 ps
CPU time 1.17 seconds
Started Jun 07 08:33:56 PM PDT 24
Finished Jun 07 08:34:02 PM PDT 24
Peak memory 218036 kb
Host smart-783152a8-e9b5-4b82-9ca2-d9c566294476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163879934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.4163879934
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert.2060205901
Short name T180
Test name
Test status
Simulation time 217534350 ps
CPU time 1.13 seconds
Started Jun 07 08:33:35 PM PDT 24
Finished Jun 07 08:33:42 PM PDT 24
Peak memory 220268 kb
Host smart-60af4d9d-bb8c-43a7-87ea-ad358450ac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060205901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2060205901
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert.2261014131
Short name T28
Test name
Test status
Simulation time 22827182 ps
CPU time 1.24 seconds
Started Jun 07 08:33:04 PM PDT 24
Finished Jun 07 08:33:08 PM PDT 24
Peak memory 219524 kb
Host smart-245ba714-0e73-48a0-bb0c-68b7587af7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261014131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2261014131
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/9.edn_disable.1030224124
Short name T21
Test name
Test status
Simulation time 31478074 ps
CPU time 0.79 seconds
Started Jun 07 08:33:09 PM PDT 24
Finished Jun 07 08:33:13 PM PDT 24
Peak memory 216152 kb
Host smart-d9cdf265-afd7-4caf-a128-12dd140b3fa8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030224124 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1030224124
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/210.edn_genbits.3624044829
Short name T379
Test name
Test status
Simulation time 86749625 ps
CPU time 1.33 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:28 PM PDT 24
Peak memory 219760 kb
Host smart-62ad1dc1-24a0-4435-90b3-51a4c267fd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624044829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3624044829
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1740591668
Short name T98
Test name
Test status
Simulation time 16511993452 ps
CPU time 417.63 seconds
Started Jun 07 08:33:29 PM PDT 24
Finished Jun 07 08:40:35 PM PDT 24
Peak memory 218220 kb
Host smart-4df83212-9de6-4861-857f-fc03e42b9f90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740591668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1740591668
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_alert_test.3706552255
Short name T339
Test name
Test status
Simulation time 144368952 ps
CPU time 0.86 seconds
Started Jun 07 08:33:17 PM PDT 24
Finished Jun 07 08:33:21 PM PDT 24
Peak memory 206576 kb
Host smart-fc0c9a9a-a643-4235-a987-c937683732f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706552255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3706552255
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/157.edn_genbits.1703159375
Short name T284
Test name
Test status
Simulation time 43472762 ps
CPU time 1.44 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 219700 kb
Host smart-5b5713e3-81d9-4eba-8c2e-299ff5738777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703159375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1703159375
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.285855740
Short name T210
Test name
Test status
Simulation time 51737465220 ps
CPU time 1100.75 seconds
Started Jun 07 08:33:05 PM PDT 24
Finished Jun 07 08:51:29 PM PDT 24
Peak memory 220712 kb
Host smart-1b63202b-ce55-46d9-bcba-663df72ba06b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285855740 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.285855740
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1244147002
Short name T283
Test name
Test status
Simulation time 146587430 ps
CPU time 1.15 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 217004 kb
Host smart-3442e446-42a5-4481-9c38-dd49edc29660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244147002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1244147002
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3352216970
Short name T310
Test name
Test status
Simulation time 215429820 ps
CPU time 2.8 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 219180 kb
Host smart-858f2535-e65a-47d4-9380-d4faa7bc6add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352216970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3352216970
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3315037437
Short name T84
Test name
Test status
Simulation time 109603896 ps
CPU time 0.8 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:33:35 PM PDT 24
Peak memory 215504 kb
Host smart-7d34f14e-53fe-42ac-afa0-2204dc76ad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315037437 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3315037437
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2139192718
Short name T237
Test name
Test status
Simulation time 31226286 ps
CPU time 1.28 seconds
Started Jun 07 08:11:39 PM PDT 24
Finished Jun 07 08:11:45 PM PDT 24
Peak memory 206340 kb
Host smart-af2d245b-042f-4962-9316-d0205031192c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139192718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2139192718
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/280.edn_genbits.242660949
Short name T81
Test name
Test status
Simulation time 47293998 ps
CPU time 1.71 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:36 PM PDT 24
Peak memory 218376 kb
Host smart-1d056175-5ddd-4e1b-b329-6dc94cca2787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242660949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.242660949
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.825905593
Short name T968
Test name
Test status
Simulation time 148089896 ps
CPU time 2.76 seconds
Started Jun 07 08:11:53 PM PDT 24
Finished Jun 07 08:12:01 PM PDT 24
Peak memory 206472 kb
Host smart-dd500791-5416-45c0-a596-598b274ace03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825905593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.825905593
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_regwen.2245998176
Short name T273
Test name
Test status
Simulation time 17351150 ps
CPU time 0.95 seconds
Started Jun 07 08:32:40 PM PDT 24
Finished Jun 07 08:32:51 PM PDT 24
Peak memory 207088 kb
Host smart-10d35e25-5349-47c3-86f7-30372a9493d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245998176 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2245998176
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_stress_all.4256429128
Short name T520
Test name
Test status
Simulation time 203169684 ps
CPU time 4.05 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 218200 kb
Host smart-2e28eb3d-f906-4e9a-ba54-d7bfd3d7b734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256429128 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4256429128
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/108.edn_genbits.3947269018
Short name T709
Test name
Test status
Simulation time 33419427 ps
CPU time 1.31 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 218372 kb
Host smart-6297044b-1923-4152-b5f2-14fa3e56b80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947269018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3947269018
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1570316006
Short name T40
Test name
Test status
Simulation time 57848831 ps
CPU time 1.26 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 218148 kb
Host smart-4ef0f390-4d2b-4ef2-b66d-e5a64476912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570316006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1570316006
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2127627408
Short name T293
Test name
Test status
Simulation time 61285788 ps
CPU time 1.32 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 219416 kb
Host smart-2a44e8c7-21de-4386-97a2-031dc453188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127627408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2127627408
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/150.edn_genbits.744474976
Short name T19
Test name
Test status
Simulation time 73709299 ps
CPU time 1.2 seconds
Started Jun 07 08:34:20 PM PDT 24
Finished Jun 07 08:34:31 PM PDT 24
Peak memory 218464 kb
Host smart-a6b400a1-fe16-4f6e-882c-79cca63926a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744474976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.744474976
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.236566117
Short name T282
Test name
Test status
Simulation time 96683328 ps
CPU time 1.18 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 219624 kb
Host smart-c3711cbb-01e9-466f-bbcd-5017759a75c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236566117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.236566117
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1996520795
Short name T300
Test name
Test status
Simulation time 30063510 ps
CPU time 1.38 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 218184 kb
Host smart-3165b74e-9706-411f-9dd5-76a5fef35622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996520795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1996520795
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1205495537
Short name T279
Test name
Test status
Simulation time 45800403 ps
CPU time 1.37 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:40 PM PDT 24
Peak memory 217136 kb
Host smart-81d3b161-2326-44e3-b39a-17a15989c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205495537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1205495537
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3252271066
Short name T298
Test name
Test status
Simulation time 63029341 ps
CPU time 1.29 seconds
Started Jun 07 08:34:31 PM PDT 24
Finished Jun 07 08:34:42 PM PDT 24
Peak memory 219008 kb
Host smart-d5483556-6d66-4f03-8859-9405e0396985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252271066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3252271066
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_alert.592806337
Short name T274
Test name
Test status
Simulation time 26335217 ps
CPU time 1.14 seconds
Started Jun 07 08:33:47 PM PDT 24
Finished Jun 07 08:33:50 PM PDT 24
Peak memory 218032 kb
Host smart-972a7c67-e5c8-4448-ac7a-fbbcc0afee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592806337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.592806337
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/43.edn_genbits.4148157332
Short name T46
Test name
Test status
Simulation time 109311388 ps
CPU time 1.48 seconds
Started Jun 07 08:34:03 PM PDT 24
Finished Jun 07 08:34:10 PM PDT 24
Peak memory 218564 kb
Host smart-a7aa23b9-cbe3-4045-a33e-811646dc0f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148157332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4148157332
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2978036415
Short name T32
Test name
Test status
Simulation time 24947340 ps
CPU time 0.95 seconds
Started Jun 07 08:33:04 PM PDT 24
Finished Jun 07 08:33:09 PM PDT 24
Peak memory 215920 kb
Host smart-805bf116-176f-4f3e-aca7-61d485241441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978036415 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2978036415
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/10.edn_err.1560461988
Short name T7
Test name
Test status
Simulation time 24056450 ps
CPU time 1.18 seconds
Started Jun 07 08:32:52 PM PDT 24
Finished Jun 07 08:32:58 PM PDT 24
Peak memory 219532 kb
Host smart-9f2ed6fb-23e3-4daf-bfae-1248eb5e3c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560461988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1560461988
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1691475541
Short name T241
Test name
Test status
Simulation time 34029607 ps
CPU time 1.23 seconds
Started Jun 07 08:11:33 PM PDT 24
Finished Jun 07 08:11:36 PM PDT 24
Peak memory 206356 kb
Host smart-0e66da52-6c75-492a-b274-61af0cf84b07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691475541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1691475541
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.828861096
Short name T949
Test name
Test status
Simulation time 61692755 ps
CPU time 3.26 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:11:42 PM PDT 24
Peak memory 206448 kb
Host smart-04666398-bc27-4c08-a0a0-9991a41d479a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828861096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.828861096
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1327031533
Short name T261
Test name
Test status
Simulation time 11852276 ps
CPU time 0.87 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:38 PM PDT 24
Peak memory 206356 kb
Host smart-fda6a704-587c-451f-a3f0-9a1a65f2b8e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327031533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1327031533
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3697307639
Short name T900
Test name
Test status
Simulation time 62509375 ps
CPU time 1.46 seconds
Started Jun 07 08:11:37 PM PDT 24
Finished Jun 07 08:11:41 PM PDT 24
Peak memory 214732 kb
Host smart-3fe569a0-4513-4464-a959-70c423a08ffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697307639 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3697307639
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.108376027
Short name T957
Test name
Test status
Simulation time 217593644 ps
CPU time 0.92 seconds
Started Jun 07 08:11:39 PM PDT 24
Finished Jun 07 08:11:43 PM PDT 24
Peak memory 206320 kb
Host smart-70793469-9d8c-4a01-b842-85d09f01e2b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108376027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.108376027
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1461561239
Short name T869
Test name
Test status
Simulation time 15029825 ps
CPU time 0.94 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:37 PM PDT 24
Peak memory 206216 kb
Host smart-270827ba-9ff1-4bac-8d31-26966f3173df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461561239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1461561239
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3093021286
Short name T870
Test name
Test status
Simulation time 38086784 ps
CPU time 1.68 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:11:39 PM PDT 24
Peak memory 214824 kb
Host smart-90481953-4fea-49de-9ff5-19ca3d160606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093021286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3093021286
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1728908646
Short name T268
Test name
Test status
Simulation time 344673438 ps
CPU time 2.6 seconds
Started Jun 07 08:11:39 PM PDT 24
Finished Jun 07 08:11:45 PM PDT 24
Peak memory 206540 kb
Host smart-34fe565b-ac98-4700-a676-9b0a77741fab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728908646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1728908646
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4182439976
Short name T230
Test name
Test status
Simulation time 57976520 ps
CPU time 1.71 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 206328 kb
Host smart-bd773b80-89b7-4da1-865b-1327af1b4768
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182439976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4182439976
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1335726643
Short name T249
Test name
Test status
Simulation time 503473744 ps
CPU time 6.29 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:43 PM PDT 24
Peak memory 206352 kb
Host smart-3f7bc915-b26e-412a-8b9f-17a2057432d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335726643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1335726643
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1476191530
Short name T941
Test name
Test status
Simulation time 27471927 ps
CPU time 0.86 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:38 PM PDT 24
Peak memory 206292 kb
Host smart-bafcbeec-9af4-40fb-82f9-836b336b15b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476191530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1476191530
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2166249425
Short name T947
Test name
Test status
Simulation time 48829785 ps
CPU time 1.08 seconds
Started Jun 07 08:11:39 PM PDT 24
Finished Jun 07 08:11:43 PM PDT 24
Peak memory 214768 kb
Host smart-4f4ae799-c838-4767-ba4a-8dcf00e674f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166249425 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2166249425
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1487637774
Short name T885
Test name
Test status
Simulation time 23455480 ps
CPU time 0.9 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:38 PM PDT 24
Peak memory 206352 kb
Host smart-94e267e6-955a-4610-980e-19bde51978d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487637774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1487637774
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3320057673
Short name T850
Test name
Test status
Simulation time 38215935 ps
CPU time 0.84 seconds
Started Jun 07 08:11:35 PM PDT 24
Finished Jun 07 08:11:37 PM PDT 24
Peak memory 206256 kb
Host smart-5f80a1bf-a0f5-4f1f-8b26-8309534e6e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320057673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3320057673
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1782760438
Short name T235
Test name
Test status
Simulation time 143432873 ps
CPU time 1.44 seconds
Started Jun 07 08:11:37 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 206460 kb
Host smart-33dde2b8-9de0-4a35-9077-3c45949cee8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782760438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1782760438
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.374443969
Short name T937
Test name
Test status
Simulation time 107341385 ps
CPU time 3.46 seconds
Started Jun 07 08:11:39 PM PDT 24
Finished Jun 07 08:11:47 PM PDT 24
Peak memory 214716 kb
Host smart-ae6eb840-ebb6-4e8f-9849-e1ca1bf9a911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374443969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.374443969
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2728731356
Short name T905
Test name
Test status
Simulation time 47031900 ps
CPU time 1.72 seconds
Started Jun 07 08:11:39 PM PDT 24
Finished Jun 07 08:11:44 PM PDT 24
Peak memory 206392 kb
Host smart-6edcaddb-deb1-4ad7-99c6-d793e19bac27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728731356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2728731356
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4102199672
Short name T966
Test name
Test status
Simulation time 206818818 ps
CPU time 1.44 seconds
Started Jun 07 08:11:53 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 214688 kb
Host smart-0fe4c6f8-1d8b-459a-96ac-d2d659f45dec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102199672 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4102199672
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3210222760
Short name T977
Test name
Test status
Simulation time 57935859 ps
CPU time 0.98 seconds
Started Jun 07 08:11:54 PM PDT 24
Finished Jun 07 08:12:01 PM PDT 24
Peak memory 206340 kb
Host smart-de68c507-664a-4ffd-95ad-e9f8d2399ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210222760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3210222760
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1814024275
Short name T878
Test name
Test status
Simulation time 29532035 ps
CPU time 0.8 seconds
Started Jun 07 08:11:51 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 206052 kb
Host smart-ac7023f5-4abc-4e90-abf2-320c77671057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814024275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1814024275
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1197187948
Short name T251
Test name
Test status
Simulation time 74574574 ps
CPU time 1.07 seconds
Started Jun 07 08:11:53 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 206444 kb
Host smart-cb8d058e-754d-484a-b1c7-a34a57d83901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197187948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1197187948
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2060871634
Short name T881
Test name
Test status
Simulation time 176826543 ps
CPU time 3.43 seconds
Started Jun 07 08:11:52 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 214784 kb
Host smart-85562658-45a3-4132-b27d-5451d517184d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060871634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2060871634
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2656653713
Short name T936
Test name
Test status
Simulation time 77045725 ps
CPU time 1.55 seconds
Started Jun 07 08:11:57 PM PDT 24
Finished Jun 07 08:12:04 PM PDT 24
Peak memory 206484 kb
Host smart-a1e8de73-0033-4d4f-b7a6-199617ae3d12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656653713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2656653713
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2740681375
Short name T856
Test name
Test status
Simulation time 50416937 ps
CPU time 0.98 seconds
Started Jun 07 08:11:52 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 206456 kb
Host smart-17c14c1e-7468-4026-9c13-e233767769de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740681375 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2740681375
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3194099204
Short name T964
Test name
Test status
Simulation time 11273647 ps
CPU time 0.93 seconds
Started Jun 07 08:11:52 PM PDT 24
Finished Jun 07 08:11:58 PM PDT 24
Peak memory 206320 kb
Host smart-20ee0965-5b91-4a04-9326-a747f4a6699f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194099204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3194099204
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1375300930
Short name T853
Test name
Test status
Simulation time 23879983 ps
CPU time 0.87 seconds
Started Jun 07 08:11:53 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 206368 kb
Host smart-cc922cf6-b423-48b7-bbab-c0b1fc11b803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375300930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1375300930
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1752636635
Short name T916
Test name
Test status
Simulation time 22261016 ps
CPU time 0.96 seconds
Started Jun 07 08:11:55 PM PDT 24
Finished Jun 07 08:12:01 PM PDT 24
Peak memory 206296 kb
Host smart-7f172281-e9c5-4b19-9f00-3bfb4a690908
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752636635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1752636635
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1625044673
Short name T855
Test name
Test status
Simulation time 114393920 ps
CPU time 3.88 seconds
Started Jun 07 08:11:57 PM PDT 24
Finished Jun 07 08:12:06 PM PDT 24
Peak memory 214688 kb
Host smart-da45a813-ad9d-4076-8f80-2f7784018ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625044673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1625044673
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1812588519
Short name T911
Test name
Test status
Simulation time 32889599 ps
CPU time 1.43 seconds
Started Jun 07 08:11:58 PM PDT 24
Finished Jun 07 08:12:04 PM PDT 24
Peak memory 214696 kb
Host smart-c40542b7-6027-4cc1-9076-b9d5baa4ebc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812588519 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1812588519
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.586784367
Short name T874
Test name
Test status
Simulation time 39468198 ps
CPU time 0.84 seconds
Started Jun 07 08:11:55 PM PDT 24
Finished Jun 07 08:12:01 PM PDT 24
Peak memory 206072 kb
Host smart-a00a7177-1351-4925-a19a-94e1874de48d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586784367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.586784367
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.622432946
Short name T859
Test name
Test status
Simulation time 14441896 ps
CPU time 0.9 seconds
Started Jun 07 08:11:49 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 206260 kb
Host smart-42b5e576-f6c0-4430-94ee-714964c666f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622432946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.622432946
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4255751947
Short name T253
Test name
Test status
Simulation time 104329873 ps
CPU time 0.95 seconds
Started Jun 07 08:11:48 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 206420 kb
Host smart-7557ad4d-cdad-469c-b2ce-de4fcde48fe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255751947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4255751947
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1891649602
Short name T858
Test name
Test status
Simulation time 644398398 ps
CPU time 4.41 seconds
Started Jun 07 08:11:52 PM PDT 24
Finished Jun 07 08:12:02 PM PDT 24
Peak memory 214648 kb
Host smart-3fc2cfbb-24fc-41f3-b1d3-b8f7afd9c55a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891649602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1891649602
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2289901694
Short name T921
Test name
Test status
Simulation time 40038469 ps
CPU time 1.11 seconds
Started Jun 07 08:12:01 PM PDT 24
Finished Jun 07 08:12:07 PM PDT 24
Peak memory 214756 kb
Host smart-9d4d9dc6-2155-46a0-b9ab-b34b9bd3ce0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289901694 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2289901694
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.697775626
Short name T923
Test name
Test status
Simulation time 12225865 ps
CPU time 0.85 seconds
Started Jun 07 08:11:58 PM PDT 24
Finished Jun 07 08:12:04 PM PDT 24
Peak memory 206332 kb
Host smart-d6dd3f30-1ad4-4336-b075-05110899a735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697775626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.697775626
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.385368490
Short name T890
Test name
Test status
Simulation time 56983651 ps
CPU time 0.88 seconds
Started Jun 07 08:11:57 PM PDT 24
Finished Jun 07 08:12:03 PM PDT 24
Peak memory 206284 kb
Host smart-937e4d99-6537-4e1a-a859-f81f700616f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385368490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.385368490
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2726395588
Short name T897
Test name
Test status
Simulation time 132146941 ps
CPU time 1.43 seconds
Started Jun 07 08:11:59 PM PDT 24
Finished Jun 07 08:12:06 PM PDT 24
Peak memory 206412 kb
Host smart-a9e3dc79-21c2-473c-b59e-3039035fcd1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726395588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2726395588
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.14278814
Short name T944
Test name
Test status
Simulation time 43765647 ps
CPU time 1.88 seconds
Started Jun 07 08:11:58 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 214736 kb
Host smart-e8d9e73b-fe12-4bd1-aabd-dd6026d91dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14278814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.14278814
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3715791670
Short name T888
Test name
Test status
Simulation time 141858479 ps
CPU time 2.18 seconds
Started Jun 07 08:11:52 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 206516 kb
Host smart-a53a351d-b16a-44d9-9941-95fc41971bde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715791670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3715791670
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2928569176
Short name T945
Test name
Test status
Simulation time 83557107 ps
CPU time 1.23 seconds
Started Jun 07 08:12:00 PM PDT 24
Finished Jun 07 08:12:06 PM PDT 24
Peak memory 214684 kb
Host smart-892050cc-4463-4e99-a62d-0138c96dba99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928569176 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2928569176
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1603488135
Short name T882
Test name
Test status
Simulation time 53800632 ps
CPU time 0.91 seconds
Started Jun 07 08:11:58 PM PDT 24
Finished Jun 07 08:12:04 PM PDT 24
Peak memory 206248 kb
Host smart-5dd4d434-8da1-430b-9c73-63701794d24d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603488135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1603488135
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1246435791
Short name T951
Test name
Test status
Simulation time 13974992 ps
CPU time 0.92 seconds
Started Jun 07 08:12:01 PM PDT 24
Finished Jun 07 08:12:06 PM PDT 24
Peak memory 206288 kb
Host smart-dcdb1210-9bca-40b9-b084-60953e419a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246435791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1246435791
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.96774226
Short name T893
Test name
Test status
Simulation time 139064912 ps
CPU time 1.44 seconds
Started Jun 07 08:11:58 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 206388 kb
Host smart-b3bcd830-912d-4ab9-8123-be41b640b4cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96774226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_out
standing.96774226
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3262152274
Short name T971
Test name
Test status
Simulation time 110624499 ps
CPU time 4.09 seconds
Started Jun 07 08:12:00 PM PDT 24
Finished Jun 07 08:12:09 PM PDT 24
Peak memory 218676 kb
Host smart-65c8286b-d743-45d8-b9d8-f8720a4c1056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262152274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3262152274
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3702028668
Short name T959
Test name
Test status
Simulation time 80620106 ps
CPU time 2.12 seconds
Started Jun 07 08:11:58 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 206472 kb
Host smart-df092eae-291a-4622-801a-facd6d54dd24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702028668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3702028668
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.44815151
Short name T976
Test name
Test status
Simulation time 20248055 ps
CPU time 1.36 seconds
Started Jun 07 08:11:59 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 214848 kb
Host smart-d0abccf3-db69-4c47-b765-61513b8fcfa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44815151 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.44815151
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2862396654
Short name T248
Test name
Test status
Simulation time 16643468 ps
CPU time 0.96 seconds
Started Jun 07 08:11:59 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 206340 kb
Host smart-c54003da-6a1c-4d51-a3d6-7f42d8d04231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862396654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2862396654
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2118992172
Short name T872
Test name
Test status
Simulation time 40250485 ps
CPU time 0.82 seconds
Started Jun 07 08:11:59 PM PDT 24
Finished Jun 07 08:12:04 PM PDT 24
Peak memory 206260 kb
Host smart-2f53f6e8-e4a5-4987-9f46-9b520ffc47ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118992172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2118992172
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3336380983
Short name T934
Test name
Test status
Simulation time 38525644 ps
CPU time 1.1 seconds
Started Jun 07 08:12:00 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 206576 kb
Host smart-3fc54dea-f95e-4f62-8f47-7395a68a04fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336380983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3336380983
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.964823543
Short name T851
Test name
Test status
Simulation time 229115521 ps
CPU time 2.35 seconds
Started Jun 07 08:11:59 PM PDT 24
Finished Jun 07 08:12:06 PM PDT 24
Peak memory 214704 kb
Host smart-ed897582-57b2-426a-a63b-466d7f04c889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964823543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.964823543
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1024010435
Short name T967
Test name
Test status
Simulation time 354239722 ps
CPU time 2.25 seconds
Started Jun 07 08:12:01 PM PDT 24
Finished Jun 07 08:12:08 PM PDT 24
Peak memory 214616 kb
Host smart-88ea862d-4ecd-40da-ad82-e13c3817ed71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024010435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1024010435
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1041016648
Short name T960
Test name
Test status
Simulation time 30023702 ps
CPU time 1.15 seconds
Started Jun 07 08:12:00 PM PDT 24
Finished Jun 07 08:12:06 PM PDT 24
Peak memory 214680 kb
Host smart-0961cbad-acb7-4f34-a9c2-6059b2cef8aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041016648 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1041016648
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3211745090
Short name T865
Test name
Test status
Simulation time 46656069 ps
CPU time 0.84 seconds
Started Jun 07 08:11:59 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 206328 kb
Host smart-f00175ca-be31-46e3-8d48-634d54578cc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211745090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3211745090
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3251590508
Short name T948
Test name
Test status
Simulation time 64157392 ps
CPU time 0.8 seconds
Started Jun 07 08:12:00 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 206008 kb
Host smart-1ead9b93-3504-44c7-8415-3e53a2e1e26f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251590508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3251590508
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.22044456
Short name T895
Test name
Test status
Simulation time 44837765 ps
CPU time 0.94 seconds
Started Jun 07 08:12:02 PM PDT 24
Finished Jun 07 08:12:07 PM PDT 24
Peak memory 206520 kb
Host smart-b0a9f9fb-846b-48c8-8077-2d6b7219f8fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_out
standing.22044456
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1617906990
Short name T973
Test name
Test status
Simulation time 109085071 ps
CPU time 2.91 seconds
Started Jun 07 08:12:00 PM PDT 24
Finished Jun 07 08:12:07 PM PDT 24
Peak memory 214608 kb
Host smart-fea5a2ef-e14a-4962-894f-cd9fbcd2f0fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617906990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1617906990
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.588177639
Short name T264
Test name
Test status
Simulation time 175618625 ps
CPU time 1.68 seconds
Started Jun 07 08:12:02 PM PDT 24
Finished Jun 07 08:12:07 PM PDT 24
Peak memory 214696 kb
Host smart-890717a6-5145-4354-bf60-c386b053bdb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588177639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.588177639
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3925638637
Short name T904
Test name
Test status
Simulation time 131443102 ps
CPU time 1.64 seconds
Started Jun 07 08:12:04 PM PDT 24
Finished Jun 07 08:12:10 PM PDT 24
Peak memory 214684 kb
Host smart-b5a53016-0a0c-420d-86a1-a3593ca80522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925638637 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3925638637
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1673468088
Short name T922
Test name
Test status
Simulation time 35352644 ps
CPU time 0.91 seconds
Started Jun 07 08:12:02 PM PDT 24
Finished Jun 07 08:12:07 PM PDT 24
Peak memory 206352 kb
Host smart-f2d1610f-6e19-4539-9cb2-8a1ef54e4d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673468088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1673468088
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1297194923
Short name T915
Test name
Test status
Simulation time 34963856 ps
CPU time 0.84 seconds
Started Jun 07 08:12:00 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 206008 kb
Host smart-44b99a39-8177-456c-aaff-15a72b3b4fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297194923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1297194923
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2577094802
Short name T935
Test name
Test status
Simulation time 57191888 ps
CPU time 1.37 seconds
Started Jun 07 08:12:01 PM PDT 24
Finished Jun 07 08:12:07 PM PDT 24
Peak memory 206476 kb
Host smart-ea71a805-e3d1-4ea5-8382-9cc54bee2cd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577094802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2577094802
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3948084040
Short name T903
Test name
Test status
Simulation time 108891934 ps
CPU time 2.89 seconds
Started Jun 07 08:11:59 PM PDT 24
Finished Jun 07 08:12:07 PM PDT 24
Peak memory 214732 kb
Host smart-96aefd40-83c9-4795-bab5-bdd9ddece7ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948084040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3948084040
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.895337586
Short name T269
Test name
Test status
Simulation time 326247518 ps
CPU time 2.37 seconds
Started Jun 07 08:12:00 PM PDT 24
Finished Jun 07 08:12:07 PM PDT 24
Peak memory 206424 kb
Host smart-e048cea4-7c0d-484d-b66e-8a3a58cdddaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895337586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.895337586
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1641279315
Short name T871
Test name
Test status
Simulation time 43089729 ps
CPU time 0.98 seconds
Started Jun 07 08:12:07 PM PDT 24
Finished Jun 07 08:12:13 PM PDT 24
Peak memory 206412 kb
Host smart-48b27b44-86ad-415b-9bb1-3190d5dd43c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641279315 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1641279315
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1194042068
Short name T255
Test name
Test status
Simulation time 87346982 ps
CPU time 0.87 seconds
Started Jun 07 08:11:59 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 206316 kb
Host smart-3821630d-77bd-48a0-ac4a-146c4d437fc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194042068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1194042068
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4068316192
Short name T920
Test name
Test status
Simulation time 33874929 ps
CPU time 0.82 seconds
Started Jun 07 08:12:03 PM PDT 24
Finished Jun 07 08:12:08 PM PDT 24
Peak memory 206076 kb
Host smart-6a00e73c-46b5-4c3a-af18-3fd6609f3ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068316192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4068316192
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4190484745
Short name T233
Test name
Test status
Simulation time 39200531 ps
CPU time 1.07 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 206340 kb
Host smart-dae57850-816b-49bb-82a2-278224dd5334
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190484745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4190484745
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1634399458
Short name T886
Test name
Test status
Simulation time 55137298 ps
CPU time 2.35 seconds
Started Jun 07 08:12:02 PM PDT 24
Finished Jun 07 08:12:08 PM PDT 24
Peak memory 214700 kb
Host smart-0ad54d6e-d6fb-430d-8586-0d363a4023a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634399458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1634399458
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.80595377
Short name T898
Test name
Test status
Simulation time 272741319 ps
CPU time 1.68 seconds
Started Jun 07 08:12:00 PM PDT 24
Finished Jun 07 08:12:06 PM PDT 24
Peak memory 214620 kb
Host smart-8af1f7e3-15c8-407e-a6f0-eef84781982d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80595377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.80595377
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4046695174
Short name T909
Test name
Test status
Simulation time 66098928 ps
CPU time 1.11 seconds
Started Jun 07 08:12:04 PM PDT 24
Finished Jun 07 08:12:10 PM PDT 24
Peak memory 214680 kb
Host smart-750553c3-bb07-4a20-922b-df594c0b19c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046695174 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.4046695174
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3424792162
Short name T238
Test name
Test status
Simulation time 129933812 ps
CPU time 0.87 seconds
Started Jun 07 08:11:59 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 206336 kb
Host smart-af16bf9f-69b1-452d-8264-fa14e86c8a03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424792162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3424792162
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2780449395
Short name T930
Test name
Test status
Simulation time 15563529 ps
CPU time 0.92 seconds
Started Jun 07 08:12:04 PM PDT 24
Finished Jun 07 08:12:09 PM PDT 24
Peak memory 206252 kb
Host smart-a2a6f3d7-b5ae-473d-b0f6-d51031e11fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780449395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2780449395
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4239080032
Short name T955
Test name
Test status
Simulation time 17421445 ps
CPU time 1.15 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:12 PM PDT 24
Peak memory 206420 kb
Host smart-df3091e9-b2a8-44d7-aca7-bce9eb63a24a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239080032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4239080032
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.436667464
Short name T956
Test name
Test status
Simulation time 96810485 ps
CPU time 2.72 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:13 PM PDT 24
Peak memory 214596 kb
Host smart-48353ce2-99e6-404b-b853-fd9958f4ebb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436667464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.436667464
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1630686303
Short name T887
Test name
Test status
Simulation time 319717734 ps
CPU time 2.37 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:13 PM PDT 24
Peak memory 214688 kb
Host smart-273d77ad-e655-447f-889b-7a3b9986da08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630686303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1630686303
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3925910725
Short name T232
Test name
Test status
Simulation time 87391431 ps
CPU time 1.62 seconds
Started Jun 07 08:11:48 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 206332 kb
Host smart-b68d057d-5bba-44c6-99fd-72165e9ad41e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925910725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3925910725
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4102520344
Short name T932
Test name
Test status
Simulation time 596199716 ps
CPU time 3.68 seconds
Started Jun 07 08:11:46 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 206332 kb
Host smart-650d6ee2-900c-4d9d-8b6f-2f4dd864f5b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102520344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4102520344
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.288977263
Short name T244
Test name
Test status
Simulation time 32172075 ps
CPU time 0.97 seconds
Started Jun 07 08:11:47 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 206452 kb
Host smart-3f996382-5870-46b8-adf6-2d3e848581f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288977263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.288977263
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2557511052
Short name T927
Test name
Test status
Simulation time 20186544 ps
CPU time 1.12 seconds
Started Jun 07 08:11:47 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 222780 kb
Host smart-5ae83aa8-a176-4b0c-adb8-04d08d10e04f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557511052 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2557511052
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2814586250
Short name T861
Test name
Test status
Simulation time 16785957 ps
CPU time 0.95 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:55 PM PDT 24
Peak memory 206304 kb
Host smart-a57aa9fa-953f-4fb2-b8fe-b9b73129b71e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814586250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2814586250
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1838774245
Short name T879
Test name
Test status
Simulation time 54056070 ps
CPU time 0.92 seconds
Started Jun 07 08:11:37 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 206208 kb
Host smart-cf6fe342-b9a1-40de-9720-799d0286e511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838774245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1838774245
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.555517939
Short name T254
Test name
Test status
Simulation time 48856664 ps
CPU time 1.04 seconds
Started Jun 07 08:11:48 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 206388 kb
Host smart-67cee4c2-2257-4ff2-905c-ccc60c33a1d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555517939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.555517939
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4289029953
Short name T914
Test name
Test status
Simulation time 45991429 ps
CPU time 2.03 seconds
Started Jun 07 08:11:36 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 214688 kb
Host smart-278585ee-ce25-49d8-a1ed-6a889a87722d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289029953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4289029953
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1529240369
Short name T270
Test name
Test status
Simulation time 451603785 ps
CPU time 2.43 seconds
Started Jun 07 08:11:41 PM PDT 24
Finished Jun 07 08:11:47 PM PDT 24
Peak memory 214584 kb
Host smart-2523bf5b-b609-44b7-841a-22d9f60d0ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529240369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1529240369
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.209848640
Short name T958
Test name
Test status
Simulation time 27833367 ps
CPU time 0.78 seconds
Started Jun 07 08:12:07 PM PDT 24
Finished Jun 07 08:12:12 PM PDT 24
Peak memory 206064 kb
Host smart-2370b7d6-a8cc-42fa-aaa0-6f37c2d4f7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209848640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.209848640
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2016470106
Short name T902
Test name
Test status
Simulation time 116022408 ps
CPU time 0.84 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 206260 kb
Host smart-ee10335f-5375-4100-9888-67f0cd5c5be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016470106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2016470106
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1639404245
Short name T868
Test name
Test status
Simulation time 12257625 ps
CPU time 0.87 seconds
Started Jun 07 08:12:10 PM PDT 24
Finished Jun 07 08:12:16 PM PDT 24
Peak memory 206276 kb
Host smart-51cb31f9-d56b-4af0-a54b-c3a06df1ba88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639404245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1639404245
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3259109149
Short name T906
Test name
Test status
Simulation time 39726943 ps
CPU time 0.85 seconds
Started Jun 07 08:12:04 PM PDT 24
Finished Jun 07 08:12:10 PM PDT 24
Peak memory 206356 kb
Host smart-c6dd6f20-9319-40e7-a9e8-7c0952c78422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259109149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3259109149
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3377852703
Short name T894
Test name
Test status
Simulation time 25088730 ps
CPU time 0.89 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 206280 kb
Host smart-e4feac22-6d25-4037-bd3a-b27608ea1cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377852703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3377852703
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.682303615
Short name T975
Test name
Test status
Simulation time 27960634 ps
CPU time 0.82 seconds
Started Jun 07 08:12:08 PM PDT 24
Finished Jun 07 08:12:14 PM PDT 24
Peak memory 206252 kb
Host smart-3793dca4-67d0-4bde-8ead-3907c41dccfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682303615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.682303615
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1042860257
Short name T972
Test name
Test status
Simulation time 55992809 ps
CPU time 0.78 seconds
Started Jun 07 08:12:12 PM PDT 24
Finished Jun 07 08:12:17 PM PDT 24
Peak memory 206076 kb
Host smart-dae26c40-73cd-479f-861e-50e09708b2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042860257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1042860257
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.340105841
Short name T913
Test name
Test status
Simulation time 13743070 ps
CPU time 0.9 seconds
Started Jun 07 08:12:07 PM PDT 24
Finished Jun 07 08:12:12 PM PDT 24
Peak memory 206316 kb
Host smart-c6a0a1d7-9dcb-4171-86f3-8f4a09657e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340105841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.340105841
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2574820853
Short name T907
Test name
Test status
Simulation time 14789604 ps
CPU time 0.88 seconds
Started Jun 07 08:12:09 PM PDT 24
Finished Jun 07 08:12:14 PM PDT 24
Peak memory 206280 kb
Host smart-e09cc167-20ed-4a7c-aefa-8e4207aeb650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574820853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2574820853
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2956765354
Short name T939
Test name
Test status
Simulation time 14504052 ps
CPU time 0.89 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:12 PM PDT 24
Peak memory 206288 kb
Host smart-3ffbd322-507c-49fe-965d-7ef1153a2230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956765354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2956765354
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2734381017
Short name T236
Test name
Test status
Simulation time 33019760 ps
CPU time 1.48 seconds
Started Jun 07 08:11:47 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 206412 kb
Host smart-efa28ec7-3a3d-4c9f-8e3e-35207d71fc93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734381017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2734381017
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1639862227
Short name T925
Test name
Test status
Simulation time 1306571399 ps
CPU time 6.92 seconds
Started Jun 07 08:11:46 PM PDT 24
Finished Jun 07 08:11:57 PM PDT 24
Peak memory 206336 kb
Host smart-de2b97a1-1ec9-436b-ab48-25ad7c107a25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639862227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1639862227
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.356438763
Short name T243
Test name
Test status
Simulation time 14334498 ps
CPU time 0.98 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 206356 kb
Host smart-210c49b3-8008-43bc-9d7f-178514bf6d03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356438763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.356438763
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3962680983
Short name T943
Test name
Test status
Simulation time 107324034 ps
CPU time 1.41 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:55 PM PDT 24
Peak memory 214736 kb
Host smart-080a9ef5-2e4c-4636-bbe3-cb292e5dc627
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962680983 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3962680983
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1007017544
Short name T940
Test name
Test status
Simulation time 19737449 ps
CPU time 0.96 seconds
Started Jun 07 08:11:49 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 206324 kb
Host smart-566b7bb1-b83d-4f42-9830-555a98c11d08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007017544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1007017544
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2180809609
Short name T884
Test name
Test status
Simulation time 14279329 ps
CPU time 0.89 seconds
Started Jun 07 08:11:45 PM PDT 24
Finished Jun 07 08:11:50 PM PDT 24
Peak memory 206204 kb
Host smart-23a2449b-6b7a-463d-a77f-a91beea6deda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180809609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2180809609
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1950764441
Short name T252
Test name
Test status
Simulation time 15222868 ps
CPU time 1.03 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 206440 kb
Host smart-962b95e4-9bad-430d-95c6-8965363968fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950764441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1950764441
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1475787800
Short name T965
Test name
Test status
Simulation time 78730199 ps
CPU time 2.84 seconds
Started Jun 07 08:11:45 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 214736 kb
Host smart-9f6e4dff-699b-42f2-b417-4d8fe61f2d34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475787800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1475787800
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.966120644
Short name T961
Test name
Test status
Simulation time 154746369 ps
CPU time 2.45 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:57 PM PDT 24
Peak memory 214664 kb
Host smart-80cfc927-ed56-4f9c-b51b-cc57a7930a61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966120644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.966120644
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3907756231
Short name T877
Test name
Test status
Simulation time 17936607 ps
CPU time 0.97 seconds
Started Jun 07 08:12:07 PM PDT 24
Finished Jun 07 08:12:13 PM PDT 24
Peak memory 206396 kb
Host smart-3793d649-30f6-4cfc-b060-f5a7271885a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907756231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3907756231
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2751671952
Short name T974
Test name
Test status
Simulation time 21725534 ps
CPU time 0.83 seconds
Started Jun 07 08:12:05 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 206288 kb
Host smart-22ab9215-6474-461b-9f5c-5e900cb0b099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751671952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2751671952
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.927834688
Short name T953
Test name
Test status
Simulation time 140953623 ps
CPU time 0.81 seconds
Started Jun 07 08:12:11 PM PDT 24
Finished Jun 07 08:12:16 PM PDT 24
Peak memory 206072 kb
Host smart-b3c02e82-3880-4dc1-ab00-30c7affe1603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927834688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.927834688
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2045456467
Short name T919
Test name
Test status
Simulation time 165328267 ps
CPU time 0.9 seconds
Started Jun 07 08:12:03 PM PDT 24
Finished Jun 07 08:12:09 PM PDT 24
Peak memory 206268 kb
Host smart-70c9e7f0-b27a-4d92-ac41-2d275633c3d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045456467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2045456467
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.242968671
Short name T917
Test name
Test status
Simulation time 12782253 ps
CPU time 0.88 seconds
Started Jun 07 08:12:09 PM PDT 24
Finished Jun 07 08:12:15 PM PDT 24
Peak memory 206276 kb
Host smart-5a8dc467-5535-4742-9a6d-dfcdfda88c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242968671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.242968671
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.90994375
Short name T908
Test name
Test status
Simulation time 78305220 ps
CPU time 0.79 seconds
Started Jun 07 08:12:04 PM PDT 24
Finished Jun 07 08:12:09 PM PDT 24
Peak memory 206060 kb
Host smart-52203774-d836-4676-96a0-d2bfab160ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90994375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.90994375
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2414669833
Short name T938
Test name
Test status
Simulation time 108186292 ps
CPU time 0.84 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 205932 kb
Host smart-06be8d4b-491e-4cc5-9ffa-b973caa66776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414669833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2414669833
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.899276250
Short name T926
Test name
Test status
Simulation time 50863392 ps
CPU time 0.86 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 206252 kb
Host smart-a45372e5-b77f-42e7-9af8-3df1807abc60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899276250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.899276250
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3925122907
Short name T864
Test name
Test status
Simulation time 179506702 ps
CPU time 0.9 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:12 PM PDT 24
Peak memory 206256 kb
Host smart-f4178478-b380-4e9e-bac5-c00d842160a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925122907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3925122907
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3579554677
Short name T860
Test name
Test status
Simulation time 49959983 ps
CPU time 0.8 seconds
Started Jun 07 08:12:07 PM PDT 24
Finished Jun 07 08:12:12 PM PDT 24
Peak memory 206036 kb
Host smart-81d960a1-7af1-4fff-b025-4c0c46c09791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579554677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3579554677
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2467884686
Short name T901
Test name
Test status
Simulation time 368599239 ps
CPU time 3.32 seconds
Started Jun 07 08:11:46 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 206360 kb
Host smart-2ae00a5b-1d3c-41bb-82a7-48802ca9118b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467884686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2467884686
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1680187701
Short name T239
Test name
Test status
Simulation time 16800377 ps
CPU time 0.96 seconds
Started Jun 07 08:11:45 PM PDT 24
Finished Jun 07 08:11:50 PM PDT 24
Peak memory 206364 kb
Host smart-5487f45c-f578-4f25-9fad-c8514590d83c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680187701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1680187701
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1532087638
Short name T946
Test name
Test status
Simulation time 463846113 ps
CPU time 1.86 seconds
Started Jun 07 08:11:52 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 214840 kb
Host smart-2b50b575-355f-4b33-9dda-f07a47ad8874
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532087638 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1532087638
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2942943135
Short name T246
Test name
Test status
Simulation time 31387606 ps
CPU time 0.91 seconds
Started Jun 07 08:11:48 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 206348 kb
Host smart-d1eab174-5124-4c54-b1a6-0c58a980daad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942943135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2942943135
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3971499299
Short name T950
Test name
Test status
Simulation time 49011254 ps
CPU time 0.86 seconds
Started Jun 07 08:11:48 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 206072 kb
Host smart-6f5ae7d7-b272-4aac-8df0-91cbb21b011e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971499299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3971499299
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3136339711
Short name T234
Test name
Test status
Simulation time 23738233 ps
CPU time 1.21 seconds
Started Jun 07 08:11:49 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 206420 kb
Host smart-b915efa3-590f-4cc5-82b4-ed475f26bc2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136339711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3136339711
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.360248386
Short name T852
Test name
Test status
Simulation time 291478045 ps
CPU time 2.25 seconds
Started Jun 07 08:11:47 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 214660 kb
Host smart-befe5588-f445-48ab-b97c-629f5686c865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360248386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.360248386
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3016889861
Short name T271
Test name
Test status
Simulation time 723836591 ps
CPU time 2.33 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:57 PM PDT 24
Peak memory 214620 kb
Host smart-a4759451-0357-4d95-9a77-da639d2176fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016889861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3016889861
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1941200064
Short name T929
Test name
Test status
Simulation time 14623202 ps
CPU time 0.9 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 206216 kb
Host smart-c989debd-0834-45f6-95b8-2b194627d6a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941200064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1941200064
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1230921020
Short name T899
Test name
Test status
Simulation time 39176948 ps
CPU time 0.8 seconds
Started Jun 07 08:12:09 PM PDT 24
Finished Jun 07 08:12:15 PM PDT 24
Peak memory 206076 kb
Host smart-b9a3e448-c4d2-4b6e-958d-8793c6d7dfda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230921020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1230921020
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1568189594
Short name T857
Test name
Test status
Simulation time 11439654 ps
CPU time 0.86 seconds
Started Jun 07 08:12:09 PM PDT 24
Finished Jun 07 08:12:15 PM PDT 24
Peak memory 206284 kb
Host smart-56334095-fb8e-49eb-840b-913d793be855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568189594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1568189594
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2123475148
Short name T867
Test name
Test status
Simulation time 29513737 ps
CPU time 0.8 seconds
Started Jun 07 08:12:07 PM PDT 24
Finished Jun 07 08:12:13 PM PDT 24
Peak memory 206076 kb
Host smart-2a72ce3d-6e2e-4245-9c84-a8a974a8db07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123475148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2123475148
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2384470208
Short name T931
Test name
Test status
Simulation time 18743842 ps
CPU time 0.81 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 206044 kb
Host smart-c4f2dfb5-0841-466c-9ccf-3e6c40125297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384470208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2384470208
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.4009107607
Short name T880
Test name
Test status
Simulation time 16221527 ps
CPU time 0.9 seconds
Started Jun 07 08:12:03 PM PDT 24
Finished Jun 07 08:12:08 PM PDT 24
Peak memory 206416 kb
Host smart-7cf52a9a-6add-493e-ac06-34467f5088c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009107607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.4009107607
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.23156614
Short name T963
Test name
Test status
Simulation time 13671218 ps
CPU time 0.89 seconds
Started Jun 07 08:12:06 PM PDT 24
Finished Jun 07 08:12:11 PM PDT 24
Peak memory 206176 kb
Host smart-d9f4cb94-065a-4d86-8502-7e91ce566755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23156614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.23156614
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.68251949
Short name T952
Test name
Test status
Simulation time 20542868 ps
CPU time 0.81 seconds
Started Jun 07 08:12:09 PM PDT 24
Finished Jun 07 08:12:15 PM PDT 24
Peak memory 206072 kb
Host smart-b270cd66-b972-42b2-bad5-afd1599d1980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68251949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.68251949
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.835818811
Short name T891
Test name
Test status
Simulation time 37750810 ps
CPU time 0.83 seconds
Started Jun 07 08:12:07 PM PDT 24
Finished Jun 07 08:12:12 PM PDT 24
Peak memory 206236 kb
Host smart-43adf318-cc7f-4e1b-aeed-d790c23a8180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835818811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.835818811
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2999501861
Short name T970
Test name
Test status
Simulation time 28454259 ps
CPU time 0.84 seconds
Started Jun 07 08:12:04 PM PDT 24
Finished Jun 07 08:12:10 PM PDT 24
Peak memory 206148 kb
Host smart-3c12f227-69d0-4498-86c2-635c454576d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999501861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2999501861
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1000713556
Short name T918
Test name
Test status
Simulation time 51659480 ps
CPU time 0.96 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 214660 kb
Host smart-1aa94955-82c6-4278-aed9-253083bc9eac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000713556 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1000713556
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2207131345
Short name T240
Test name
Test status
Simulation time 15842407 ps
CPU time 0.98 seconds
Started Jun 07 08:11:48 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 206364 kb
Host smart-044bda64-441c-404b-8abe-cb2fc445716b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207131345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2207131345
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3328205411
Short name T928
Test name
Test status
Simulation time 36697425 ps
CPU time 0.92 seconds
Started Jun 07 08:11:47 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 206284 kb
Host smart-6f4566e9-bf3c-4f91-96a0-105e38056531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328205411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3328205411
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1035024721
Short name T924
Test name
Test status
Simulation time 175522684 ps
CPU time 1.42 seconds
Started Jun 07 08:11:47 PM PDT 24
Finished Jun 07 08:11:52 PM PDT 24
Peak memory 206412 kb
Host smart-0c35c158-f406-4791-a011-7d0125f0e5e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035024721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1035024721
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1128300019
Short name T969
Test name
Test status
Simulation time 151444272 ps
CPU time 3.88 seconds
Started Jun 07 08:11:47 PM PDT 24
Finished Jun 07 08:11:55 PM PDT 24
Peak memory 214680 kb
Host smart-7bdbcff4-2bd2-4c82-8984-f70c797cea1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128300019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1128300019
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2295874713
Short name T267
Test name
Test status
Simulation time 44086437 ps
CPU time 1.55 seconds
Started Jun 07 08:11:48 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 206648 kb
Host smart-379e8d2a-2946-4840-a275-890196a58fd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295874713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2295874713
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4115229102
Short name T876
Test name
Test status
Simulation time 31572706 ps
CPU time 1.18 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 214692 kb
Host smart-b9e49819-29de-4600-932c-35525b1775b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115229102 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.4115229102
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3260290368
Short name T245
Test name
Test status
Simulation time 12368906 ps
CPU time 0.9 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 206352 kb
Host smart-d62e7d48-bcec-436e-b8b7-9aa5f5f8e83f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260290368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3260290368
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3849281910
Short name T854
Test name
Test status
Simulation time 39994723 ps
CPU time 0.83 seconds
Started Jun 07 08:11:53 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 206076 kb
Host smart-6a0437fb-394d-44ee-bde9-da6fdf643753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849281910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3849281910
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.876457656
Short name T256
Test name
Test status
Simulation time 69157919 ps
CPU time 1.42 seconds
Started Jun 07 08:11:49 PM PDT 24
Finished Jun 07 08:11:55 PM PDT 24
Peak memory 206464 kb
Host smart-55904fc6-6580-410b-8b98-be460a867cd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876457656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.876457656
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.4002512601
Short name T933
Test name
Test status
Simulation time 140861133 ps
CPU time 2.7 seconds
Started Jun 07 08:11:51 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 214648 kb
Host smart-75ac33ca-64ff-48ef-b0fe-2ffe4f19d2a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002512601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4002512601
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3337183414
Short name T962
Test name
Test status
Simulation time 222569641 ps
CPU time 3.07 seconds
Started Jun 07 08:11:50 PM PDT 24
Finished Jun 07 08:11:57 PM PDT 24
Peak memory 206556 kb
Host smart-46a0496c-ae30-4698-b0fa-ee069576f9bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337183414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3337183414
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.589008709
Short name T889
Test name
Test status
Simulation time 79273875 ps
CPU time 1.19 seconds
Started Jun 07 08:11:53 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 214668 kb
Host smart-57e76d9c-b235-4c64-95a4-b711818816b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589008709 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.589008709
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1933746339
Short name T250
Test name
Test status
Simulation time 15126760 ps
CPU time 0.91 seconds
Started Jun 07 08:11:56 PM PDT 24
Finished Jun 07 08:12:02 PM PDT 24
Peak memory 206268 kb
Host smart-45b6ae11-1aec-4853-b2e5-51dfe6b1d0d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933746339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1933746339
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2944364909
Short name T862
Test name
Test status
Simulation time 33981343 ps
CPU time 0.81 seconds
Started Jun 07 08:11:49 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 205944 kb
Host smart-d96309bb-00c4-4803-8486-d4c5c9807b96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944364909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2944364909
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2168451708
Short name T896
Test name
Test status
Simulation time 43267118 ps
CPU time 1.12 seconds
Started Jun 07 08:11:52 PM PDT 24
Finished Jun 07 08:11:58 PM PDT 24
Peak memory 206484 kb
Host smart-918cbdf1-a27c-400b-8e42-eae1e593c0b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168451708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2168451708
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1534709403
Short name T866
Test name
Test status
Simulation time 130072423 ps
CPU time 2.71 seconds
Started Jun 07 08:11:49 PM PDT 24
Finished Jun 07 08:11:56 PM PDT 24
Peak memory 223032 kb
Host smart-8cd21695-54c7-4239-8f8a-39a85b4edd22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534709403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1534709403
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1268608031
Short name T262
Test name
Test status
Simulation time 173025001 ps
CPU time 1.67 seconds
Started Jun 07 08:11:56 PM PDT 24
Finished Jun 07 08:12:03 PM PDT 24
Peak memory 214568 kb
Host smart-dad135dd-3242-42f4-b920-aa9b03802412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268608031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1268608031
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1216180042
Short name T912
Test name
Test status
Simulation time 19877966 ps
CPU time 1.18 seconds
Started Jun 07 08:11:55 PM PDT 24
Finished Jun 07 08:12:02 PM PDT 24
Peak memory 222852 kb
Host smart-12bc085f-1632-4e8e-a4fc-6ae78c0853b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216180042 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1216180042
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1418162999
Short name T247
Test name
Test status
Simulation time 39860260 ps
CPU time 0.93 seconds
Started Jun 07 08:11:52 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 206248 kb
Host smart-5d92c03e-7ad8-4e91-985a-c1a79ec1531a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418162999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1418162999
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1585390568
Short name T875
Test name
Test status
Simulation time 39423104 ps
CPU time 0.87 seconds
Started Jun 07 08:11:54 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 206284 kb
Host smart-706b1d9a-8906-468f-b924-5aaa9da7ab49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585390568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1585390568
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2835395422
Short name T942
Test name
Test status
Simulation time 102525501 ps
CPU time 1.27 seconds
Started Jun 07 08:11:51 PM PDT 24
Finished Jun 07 08:11:58 PM PDT 24
Peak memory 206420 kb
Host smart-425abc6c-b4b1-4fd2-af1f-83fb60f2fd50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835395422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2835395422
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3322986430
Short name T873
Test name
Test status
Simulation time 180655312 ps
CPU time 2.16 seconds
Started Jun 07 08:11:51 PM PDT 24
Finished Jun 07 08:11:57 PM PDT 24
Peak memory 214680 kb
Host smart-215c1184-3fe9-4151-b9c8-46beeca7a9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322986430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3322986430
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.293765427
Short name T910
Test name
Test status
Simulation time 50301971 ps
CPU time 1.7 seconds
Started Jun 07 08:11:54 PM PDT 24
Finished Jun 07 08:12:01 PM PDT 24
Peak memory 214556 kb
Host smart-9485b21d-19c2-49f8-8ea0-f9cb916eb3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293765427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.293765427
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3891089892
Short name T892
Test name
Test status
Simulation time 83256338 ps
CPU time 1.15 seconds
Started Jun 07 08:11:56 PM PDT 24
Finished Jun 07 08:12:03 PM PDT 24
Peak memory 214696 kb
Host smart-540fd2b2-871b-409c-abd4-b6a63e0509d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891089892 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3891089892
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.589185383
Short name T242
Test name
Test status
Simulation time 36422618 ps
CPU time 0.86 seconds
Started Jun 07 08:11:53 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 206360 kb
Host smart-fa361b5c-40d9-4e78-9e89-2e015c2dcdaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589185383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.589185383
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3156473086
Short name T883
Test name
Test status
Simulation time 89899346 ps
CPU time 0.86 seconds
Started Jun 07 08:11:53 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 206268 kb
Host smart-ec9372f7-465e-41b5-9827-e28d69eb755b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156473086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3156473086
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.964047773
Short name T954
Test name
Test status
Simulation time 15448290 ps
CPU time 1.02 seconds
Started Jun 07 08:11:53 PM PDT 24
Finished Jun 07 08:11:59 PM PDT 24
Peak memory 206424 kb
Host smart-c33d93ee-a93d-41e2-af67-340db1f29e64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964047773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.964047773
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4101790474
Short name T863
Test name
Test status
Simulation time 253998896 ps
CPU time 2.45 seconds
Started Jun 07 08:11:52 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 214648 kb
Host smart-c64326f9-5609-4fce-91ee-e9ff63ba67fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101790474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4101790474
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2992190137
Short name T263
Test name
Test status
Simulation time 337932743 ps
CPU time 2.5 seconds
Started Jun 07 08:11:55 PM PDT 24
Finished Jun 07 08:12:02 PM PDT 24
Peak memory 206356 kb
Host smart-c593a5e5-24db-4687-a174-7690c068d625
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992190137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2992190137
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.1218382192
Short name T687
Test name
Test status
Simulation time 23041901 ps
CPU time 1.03 seconds
Started Jun 07 08:32:43 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 206592 kb
Host smart-6c0a2f0e-3f00-4003-88d9-5f57ff3a5c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218382192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1218382192
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.4288740729
Short name T147
Test name
Test status
Simulation time 17191851 ps
CPU time 0.86 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:46 PM PDT 24
Peak memory 215324 kb
Host smart-4372f98f-323a-4c13-a11f-e97a081c85e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288740729 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.4288740729
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.153963156
Short name T471
Test name
Test status
Simulation time 23193506 ps
CPU time 1.28 seconds
Started Jun 07 08:32:33 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 218128 kb
Host smart-fd875708-12a2-499e-98fc-50c5c21379bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153963156 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.153963156
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1383648403
Short name T532
Test name
Test status
Simulation time 36699845 ps
CPU time 1.6 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 225620 kb
Host smart-e4f4149a-c6aa-40b4-8190-ea5c85ed2fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383648403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1383648403
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2806335792
Short name T479
Test name
Test status
Simulation time 40155044 ps
CPU time 1.58 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 218276 kb
Host smart-77b4a465-31c5-43d4-8859-33a32321120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806335792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2806335792
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2240098006
Short name T672
Test name
Test status
Simulation time 80971255 ps
CPU time 0.8 seconds
Started Jun 07 08:33:12 PM PDT 24
Finished Jun 07 08:33:15 PM PDT 24
Peak memory 215152 kb
Host smart-b06ee4a0-4421-4193-adf8-3709fc3b8200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240098006 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2240098006
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2096772739
Short name T3
Test name
Test status
Simulation time 965646670 ps
CPU time 7.85 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:56 PM PDT 24
Peak memory 237244 kb
Host smart-add162ab-1496-4534-a85d-cc43fa9e323d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096772739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2096772739
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1550212949
Short name T698
Test name
Test status
Simulation time 125206342 ps
CPU time 0.93 seconds
Started Jun 07 08:32:33 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 215208 kb
Host smart-56ef360c-1c7c-4695-a8ba-31789ae2f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550212949 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1550212949
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2462621644
Short name T216
Test name
Test status
Simulation time 52561475242 ps
CPU time 1182.26 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:52:25 PM PDT 24
Peak memory 220272 kb
Host smart-79da9a6e-877a-4366-ba58-2a09988f7caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462621644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2462621644
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.1834591911
Short name T689
Test name
Test status
Simulation time 21238130 ps
CPU time 0.99 seconds
Started Jun 07 08:32:50 PM PDT 24
Finished Jun 07 08:32:56 PM PDT 24
Peak memory 206612 kb
Host smart-1c8bab9e-e98d-47fa-99d8-23b9e5aa3bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834591911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1834591911
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.995625335
Short name T770
Test name
Test status
Simulation time 17087752 ps
CPU time 0.9 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 216280 kb
Host smart-9cc6bcd2-01a6-4d61-aac7-1d1c59338ef6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995625335 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.995625335
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1160215307
Short name T423
Test name
Test status
Simulation time 27521216 ps
CPU time 1.01 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 218244 kb
Host smart-b5a210f5-a25a-480d-914d-789d6d0d3863
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160215307 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1160215307
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.1318008886
Short name T552
Test name
Test status
Simulation time 84391199 ps
CPU time 1.39 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:42 PM PDT 24
Peak memory 218296 kb
Host smart-bd61b698-0e68-4b07-9c6e-cd4bcec25109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318008886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1318008886
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.456880944
Short name T441
Test name
Test status
Simulation time 20983128 ps
CPU time 1.05 seconds
Started Jun 07 08:32:43 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 215356 kb
Host smart-537d0d85-b228-4fd6-ac91-903f3b54548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456880944 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.456880944
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3566802442
Short name T220
Test name
Test status
Simulation time 26375261 ps
CPU time 0.89 seconds
Started Jun 07 08:32:33 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 206956 kb
Host smart-78d9073e-4db0-4eed-af9e-eefd122517f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566802442 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3566802442
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.52152989
Short name T642
Test name
Test status
Simulation time 45436251 ps
CPU time 0.93 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 215208 kb
Host smart-77736cec-48e9-4655-9644-4578ec8aa759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52152989 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.52152989
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2508142485
Short name T622
Test name
Test status
Simulation time 39554987 ps
CPU time 1.41 seconds
Started Jun 07 08:32:40 PM PDT 24
Finished Jun 07 08:32:51 PM PDT 24
Peak memory 215256 kb
Host smart-23393aea-c331-48b8-872f-bc45edc0ad37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508142485 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2508142485
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.839585287
Short name T692
Test name
Test status
Simulation time 38961991745 ps
CPU time 867.78 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:47:15 PM PDT 24
Peak memory 218068 kb
Host smart-689b4bc3-2e44-47ea-b279-003352af057f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839585287 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.839585287
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.3859013370
Short name T493
Test name
Test status
Simulation time 44926929 ps
CPU time 0.87 seconds
Started Jun 07 08:33:09 PM PDT 24
Finished Jun 07 08:33:13 PM PDT 24
Peak memory 214780 kb
Host smart-da84b07f-de9a-4b53-b113-192148bfba55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859013370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3859013370
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_genbits.792266196
Short name T229
Test name
Test status
Simulation time 59258978 ps
CPU time 1.38 seconds
Started Jun 07 08:32:58 PM PDT 24
Finished Jun 07 08:33:04 PM PDT 24
Peak memory 216816 kb
Host smart-7345cc94-9403-431a-bee4-d231c8196f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792266196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.792266196
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2939781663
Short name T676
Test name
Test status
Simulation time 38743516 ps
CPU time 1 seconds
Started Jun 07 08:33:06 PM PDT 24
Finished Jun 07 08:33:10 PM PDT 24
Peak memory 224160 kb
Host smart-a7368054-ff66-43a1-b718-d733b43f3813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939781663 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2939781663
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.228915097
Short name T590
Test name
Test status
Simulation time 91093500 ps
CPU time 0.96 seconds
Started Jun 07 08:33:05 PM PDT 24
Finished Jun 07 08:33:10 PM PDT 24
Peak memory 215280 kb
Host smart-0b52e3fc-06fc-4f34-b197-986f3f401797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228915097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.228915097
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3589610527
Short name T544
Test name
Test status
Simulation time 222344177 ps
CPU time 2.82 seconds
Started Jun 07 08:33:14 PM PDT 24
Finished Jun 07 08:33:20 PM PDT 24
Peak memory 215248 kb
Host smart-19103c79-5723-41ad-adcd-ea17f3beb05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589610527 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3589610527
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3335179664
Short name T726
Test name
Test status
Simulation time 19271982640 ps
CPU time 485.95 seconds
Started Jun 07 08:32:50 PM PDT 24
Finished Jun 07 08:41:01 PM PDT 24
Peak memory 217992 kb
Host smart-72fed9ec-f686-49f4-aed0-11fa83eea98f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335179664 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3335179664
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.549975874
Short name T768
Test name
Test status
Simulation time 68973548 ps
CPU time 1.27 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 218528 kb
Host smart-d37a939a-e8c0-4004-ac28-f60d6c81d9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549975874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.549975874
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.613940796
Short name T792
Test name
Test status
Simulation time 28056362 ps
CPU time 1.28 seconds
Started Jun 07 08:34:05 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 219736 kb
Host smart-b5931559-1108-481e-9e3f-8b16e1283271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613940796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.613940796
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.229622735
Short name T510
Test name
Test status
Simulation time 247869267 ps
CPU time 1.58 seconds
Started Jun 07 08:34:01 PM PDT 24
Finished Jun 07 08:34:08 PM PDT 24
Peak memory 218412 kb
Host smart-6fc3cfd5-10c0-4299-97ea-693cd0b15781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229622735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.229622735
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1101774109
Short name T397
Test name
Test status
Simulation time 55267536 ps
CPU time 1.39 seconds
Started Jun 07 08:33:59 PM PDT 24
Finished Jun 07 08:34:06 PM PDT 24
Peak memory 219440 kb
Host smart-92fab115-205b-4741-8c1c-5930c1dd7676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101774109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1101774109
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.398485059
Short name T474
Test name
Test status
Simulation time 43755952 ps
CPU time 1.5 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 218132 kb
Host smart-ff8611a8-c68e-4df4-a866-5a5b349f3136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398485059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.398485059
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2271657753
Short name T318
Test name
Test status
Simulation time 81251462 ps
CPU time 1.2 seconds
Started Jun 07 08:34:10 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 218384 kb
Host smart-3e43f3f3-4241-4f71-ab36-f63dc668245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271657753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2271657753
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3114692563
Short name T445
Test name
Test status
Simulation time 70115219 ps
CPU time 1.5 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:30 PM PDT 24
Peak memory 218220 kb
Host smart-93d0f8e0-54a8-476c-bacf-e8c76f646347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114692563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3114692563
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3558451869
Short name T633
Test name
Test status
Simulation time 230941883 ps
CPU time 1.42 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 218468 kb
Host smart-26bcc842-b694-4f6b-a200-81a6bfce57fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558451869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3558451869
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.860666817
Short name T554
Test name
Test status
Simulation time 38340422 ps
CPU time 1.61 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 216964 kb
Host smart-46289a13-b27a-4cd2-92ed-40dbe5f5f1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860666817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.860666817
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.3554659155
Short name T486
Test name
Test status
Simulation time 16755974 ps
CPU time 0.99 seconds
Started Jun 07 08:33:02 PM PDT 24
Finished Jun 07 08:33:06 PM PDT 24
Peak memory 206540 kb
Host smart-426033eb-b76b-4ddb-a0c9-edc854fdecde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554659155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3554659155
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2282307934
Short name T171
Test name
Test status
Simulation time 14079268 ps
CPU time 0.9 seconds
Started Jun 07 08:32:54 PM PDT 24
Finished Jun 07 08:32:59 PM PDT 24
Peak memory 216568 kb
Host smart-182cf83a-15f5-48c0-92a9-0ad9f0e6a8b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282307934 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2282307934
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.594580991
Short name T363
Test name
Test status
Simulation time 87029128 ps
CPU time 1.03 seconds
Started Jun 07 08:33:01 PM PDT 24
Finished Jun 07 08:33:05 PM PDT 24
Peak memory 218068 kb
Host smart-66c19896-778b-4c73-a5d6-11b167d4d038
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594580991 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.594580991
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1446924356
Short name T817
Test name
Test status
Simulation time 59517731 ps
CPU time 0.88 seconds
Started Jun 07 08:32:57 PM PDT 24
Finished Jun 07 08:33:02 PM PDT 24
Peak memory 218560 kb
Host smart-6d551d55-13b5-47be-8cc4-250e37f47a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446924356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1446924356
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1321600053
Short name T390
Test name
Test status
Simulation time 129465667 ps
CPU time 1.79 seconds
Started Jun 07 08:32:59 PM PDT 24
Finished Jun 07 08:33:05 PM PDT 24
Peak memory 220080 kb
Host smart-1dcd4bac-3bc8-46c7-8a7a-73c7fcfa8452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321600053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1321600053
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.424711913
Short name T529
Test name
Test status
Simulation time 24775191 ps
CPU time 0.99 seconds
Started Jun 07 08:32:56 PM PDT 24
Finished Jun 07 08:33:02 PM PDT 24
Peak memory 215900 kb
Host smart-7b4ba409-89d4-4409-a6dc-977ce45d0286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424711913 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.424711913
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4102549030
Short name T326
Test name
Test status
Simulation time 35297299 ps
CPU time 0.9 seconds
Started Jun 07 08:32:57 PM PDT 24
Finished Jun 07 08:33:02 PM PDT 24
Peak memory 215164 kb
Host smart-44fe7d36-75d8-488d-83c1-e76aab3f22dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102549030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4102549030
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1630963434
Short name T498
Test name
Test status
Simulation time 533540899 ps
CPU time 2.93 seconds
Started Jun 07 08:33:05 PM PDT 24
Finished Jun 07 08:33:11 PM PDT 24
Peak memory 216820 kb
Host smart-34249dbe-e343-4796-a056-4b172491f7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630963434 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1630963434
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2504538886
Short name T671
Test name
Test status
Simulation time 203154616220 ps
CPU time 1117.6 seconds
Started Jun 07 08:32:52 PM PDT 24
Finished Jun 07 08:51:34 PM PDT 24
Peak memory 223540 kb
Host smart-64d6165a-c1e8-4cb2-beb5-d993c28f8e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504538886 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2504538886
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2888164799
Short name T44
Test name
Test status
Simulation time 142940975 ps
CPU time 1.41 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 218312 kb
Host smart-36b680ee-d49d-4817-b710-60610caf6904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888164799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2888164799
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1997490784
Short name T335
Test name
Test status
Simulation time 354591913 ps
CPU time 1.63 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:22 PM PDT 24
Peak memory 218400 kb
Host smart-a0d7b139-1dec-41e3-9c5d-aaba631ce099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997490784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1997490784
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1418893204
Short name T436
Test name
Test status
Simulation time 42267981 ps
CPU time 1.18 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 216800 kb
Host smart-b1af30fe-1bf5-488e-a720-09ba0335b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418893204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1418893204
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.28141685
Short name T333
Test name
Test status
Simulation time 40875502 ps
CPU time 1.69 seconds
Started Jun 07 08:34:10 PM PDT 24
Finished Jun 07 08:34:17 PM PDT 24
Peak memory 218416 kb
Host smart-f9c910d3-4544-42ea-aaa0-83dbdce8461f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28141685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.28141685
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.51266217
Short name T602
Test name
Test status
Simulation time 286768201 ps
CPU time 3.79 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:20 PM PDT 24
Peak memory 218720 kb
Host smart-c59bd222-28a6-4858-bd44-51eef772765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51266217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.51266217
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.138449125
Short name T703
Test name
Test status
Simulation time 70892901 ps
CPU time 1.18 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 218524 kb
Host smart-aee0cfd0-69c4-4431-825e-9fd6fc653181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138449125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.138449125
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2242914833
Short name T653
Test name
Test status
Simulation time 42898199 ps
CPU time 1.56 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 218280 kb
Host smart-d9144a59-4366-4833-9227-50d3e22955fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242914833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2242914833
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1246639324
Short name T448
Test name
Test status
Simulation time 32118534 ps
CPU time 1.14 seconds
Started Jun 07 08:34:00 PM PDT 24
Finished Jun 07 08:34:07 PM PDT 24
Peak memory 216820 kb
Host smart-67017fb4-18ef-4a71-9181-9d977137d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246639324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1246639324
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3916442771
Short name T839
Test name
Test status
Simulation time 77140633 ps
CPU time 1.63 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 219748 kb
Host smart-3b471d2c-bbac-426b-a7bd-7892ebafa283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916442771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3916442771
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2113383125
Short name T402
Test name
Test status
Simulation time 29866386 ps
CPU time 0.95 seconds
Started Jun 07 08:33:05 PM PDT 24
Finished Jun 07 08:33:09 PM PDT 24
Peak memory 206588 kb
Host smart-85f40a1e-8144-48fd-a116-f0af4c657864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113383125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2113383125
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1885262668
Short name T186
Test name
Test status
Simulation time 11552663 ps
CPU time 0.87 seconds
Started Jun 07 08:32:49 PM PDT 24
Finished Jun 07 08:32:55 PM PDT 24
Peak memory 216300 kb
Host smart-8202056a-8207-433c-afc3-5a044b9cc8a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885262668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1885262668
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3857676007
Short name T655
Test name
Test status
Simulation time 38965710 ps
CPU time 1.17 seconds
Started Jun 07 08:33:05 PM PDT 24
Finished Jun 07 08:33:10 PM PDT 24
Peak memory 216852 kb
Host smart-828f608f-087b-4b5e-b9ca-2aca2b7feb77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857676007 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3857676007
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1090852371
Short name T169
Test name
Test status
Simulation time 21099771 ps
CPU time 0.94 seconds
Started Jun 07 08:32:51 PM PDT 24
Finished Jun 07 08:32:57 PM PDT 24
Peak memory 218488 kb
Host smart-6a74f53f-21b2-4c86-8f9d-9af8040be9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090852371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1090852371
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1533025535
Short name T490
Test name
Test status
Simulation time 227078060 ps
CPU time 1.07 seconds
Started Jun 07 08:33:01 PM PDT 24
Finished Jun 07 08:33:06 PM PDT 24
Peak memory 216984 kb
Host smart-bbd8ee1f-bf8f-455d-8a0f-340bbe7e843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533025535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1533025535
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.3392798709
Short name T401
Test name
Test status
Simulation time 17169048 ps
CPU time 1.05 seconds
Started Jun 07 08:33:06 PM PDT 24
Finished Jun 07 08:33:11 PM PDT 24
Peak memory 215280 kb
Host smart-0281c4ec-5951-4b3a-b0b2-6f9512689e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392798709 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3392798709
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3142386079
Short name T295
Test name
Test status
Simulation time 767435542 ps
CPU time 4.48 seconds
Started Jun 07 08:33:06 PM PDT 24
Finished Jun 07 08:33:14 PM PDT 24
Peak memory 216912 kb
Host smart-f4d30acb-b441-4bde-a29f-e4bf54cf0633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142386079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3142386079
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/120.edn_genbits.3601529878
Short name T796
Test name
Test status
Simulation time 145409089 ps
CPU time 1.28 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:20 PM PDT 24
Peak memory 220064 kb
Host smart-9159b7ca-bb37-4589-b04d-4c04ba11bc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601529878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3601529878
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1274826590
Short name T603
Test name
Test status
Simulation time 48535305 ps
CPU time 1.24 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 218000 kb
Host smart-75e63a82-da25-47e6-865a-f713a7d7fb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274826590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1274826590
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1068776858
Short name T836
Test name
Test status
Simulation time 136320646 ps
CPU time 1.19 seconds
Started Jun 07 08:34:05 PM PDT 24
Finished Jun 07 08:34:12 PM PDT 24
Peak memory 216848 kb
Host smart-33297bb7-b4af-4c9f-ad53-102df174e64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068776858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1068776858
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1036877679
Short name T377
Test name
Test status
Simulation time 66709022 ps
CPU time 1.2 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 219196 kb
Host smart-dbd0e6ae-9ce3-40d8-84ab-95455a31bd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036877679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1036877679
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.178661717
Short name T218
Test name
Test status
Simulation time 54513670 ps
CPU time 1.2 seconds
Started Jun 07 08:34:10 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 218328 kb
Host smart-4ac29be3-599f-4651-80a7-cd6fc5f4ef5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178661717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.178661717
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2096466034
Short name T336
Test name
Test status
Simulation time 73418455 ps
CPU time 1.2 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:22 PM PDT 24
Peak memory 216880 kb
Host smart-69bb3ab0-4aa4-4af3-acb9-d5edf33d0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096466034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2096466034
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.142624203
Short name T94
Test name
Test status
Simulation time 31553773 ps
CPU time 1.33 seconds
Started Jun 07 08:34:06 PM PDT 24
Finished Jun 07 08:34:13 PM PDT 24
Peak memory 219044 kb
Host smart-483c9d86-0537-4f5f-9cbb-c402d8551390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142624203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.142624203
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3359511779
Short name T265
Test name
Test status
Simulation time 42171809 ps
CPU time 1.44 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:25 PM PDT 24
Peak memory 218196 kb
Host smart-5e7a9891-630c-4497-b47f-2b76ab9973d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359511779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3359511779
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1441190727
Short name T542
Test name
Test status
Simulation time 93939223 ps
CPU time 1.28 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:20 PM PDT 24
Peak memory 218524 kb
Host smart-c0714e75-ea87-426a-b20a-d42244ed38be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441190727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1441190727
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2317298155
Short name T566
Test name
Test status
Simulation time 182189810 ps
CPU time 1.46 seconds
Started Jun 07 08:34:08 PM PDT 24
Finished Jun 07 08:34:14 PM PDT 24
Peak memory 218228 kb
Host smart-3f9dff9e-4ebb-4c66-94ef-f9c0686e5c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317298155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2317298155
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3574171640
Short name T156
Test name
Test status
Simulation time 44964940 ps
CPU time 1.06 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 219528 kb
Host smart-e127cbea-7e1e-4938-8120-9a74cca6c29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574171640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3574171640
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3397232493
Short name T513
Test name
Test status
Simulation time 82139570 ps
CPU time 0.91 seconds
Started Jun 07 08:33:04 PM PDT 24
Finished Jun 07 08:33:09 PM PDT 24
Peak memory 214704 kb
Host smart-bad3e1ef-90ee-4e0c-aa8b-ae3956082a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397232493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3397232493
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2416832683
Short name T353
Test name
Test status
Simulation time 24552866 ps
CPU time 1.08 seconds
Started Jun 07 08:32:58 PM PDT 24
Finished Jun 07 08:33:03 PM PDT 24
Peak memory 218052 kb
Host smart-f54e31b3-3025-41af-8797-c274e43dcdf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416832683 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2416832683
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.2822967517
Short name T462
Test name
Test status
Simulation time 65619363 ps
CPU time 1.17 seconds
Started Jun 07 08:33:01 PM PDT 24
Finished Jun 07 08:33:06 PM PDT 24
Peak memory 218604 kb
Host smart-f9d03854-4011-43f8-81c4-a1c0ab7acb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822967517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2822967517
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.1713365242
Short name T360
Test name
Test status
Simulation time 38413670 ps
CPU time 0.93 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 215220 kb
Host smart-8a2e77aa-873b-44e3-90a9-d95ba97e18c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713365242 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1713365242
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4261134569
Short name T456
Test name
Test status
Simulation time 228436851 ps
CPU time 1.89 seconds
Started Jun 07 08:33:04 PM PDT 24
Finished Jun 07 08:33:09 PM PDT 24
Peak memory 217076 kb
Host smart-12c474e9-5240-4e98-9d8f-b18675cd1fba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261134569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4261134569
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.54924836
Short name T485
Test name
Test status
Simulation time 58059247362 ps
CPU time 687.49 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:44:27 PM PDT 24
Peak memory 217856 kb
Host smart-3844ee1f-5718-473b-91eb-885db6e5d80c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54924836 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.54924836
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.edn_genbits.2165982582
Short name T407
Test name
Test status
Simulation time 46638809 ps
CPU time 1.44 seconds
Started Jun 07 08:34:17 PM PDT 24
Finished Jun 07 08:34:30 PM PDT 24
Peak memory 218180 kb
Host smart-4bafd7d1-4db7-42b3-b325-949be4eda010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165982582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2165982582
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2933561235
Short name T367
Test name
Test status
Simulation time 62095421 ps
CPU time 1.04 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 216972 kb
Host smart-a9909d74-61cb-4166-9094-2b60c1180b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933561235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2933561235
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.4172242277
Short name T426
Test name
Test status
Simulation time 86787005 ps
CPU time 1.18 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 219552 kb
Host smart-a48cd5a2-8318-4077-9bf1-6b0e96dad9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172242277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.4172242277
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2931607677
Short name T783
Test name
Test status
Simulation time 25235604 ps
CPU time 1.17 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 216808 kb
Host smart-5baafde9-dfa0-46ee-af8c-3c2affb65665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931607677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2931607677
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.494235027
Short name T413
Test name
Test status
Simulation time 49821824 ps
CPU time 1.22 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:20 PM PDT 24
Peak memory 217960 kb
Host smart-ad155adc-ee39-43c0-8769-b7d775c55797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494235027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.494235027
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1397404116
Short name T724
Test name
Test status
Simulation time 61646443 ps
CPU time 1.29 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:20 PM PDT 24
Peak memory 217968 kb
Host smart-f3e5f7d8-e0ef-49e4-b39c-0b58603036ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397404116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1397404116
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.691552055
Short name T727
Test name
Test status
Simulation time 389842833 ps
CPU time 3.49 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 219796 kb
Host smart-1f4209eb-3030-4863-8588-24ac938fe992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691552055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.691552055
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.458928950
Short name T679
Test name
Test status
Simulation time 46327980 ps
CPU time 1.66 seconds
Started Jun 07 08:34:05 PM PDT 24
Finished Jun 07 08:34:12 PM PDT 24
Peak memory 218132 kb
Host smart-4543e9e5-e317-4099-bf12-b3f4f206483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458928950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.458928950
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1563531466
Short name T710
Test name
Test status
Simulation time 87032157 ps
CPU time 1.37 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 218624 kb
Host smart-ad530de6-58d3-4472-ba54-82f1cecfc08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563531466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1563531466
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3534657936
Short name T277
Test name
Test status
Simulation time 38423222 ps
CPU time 1.24 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 218384 kb
Host smart-337834eb-7d9b-453d-9418-63b9bd09b260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534657936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3534657936
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.1613333839
Short name T581
Test name
Test status
Simulation time 40399343 ps
CPU time 0.89 seconds
Started Jun 07 08:33:10 PM PDT 24
Finished Jun 07 08:33:14 PM PDT 24
Peak memory 216224 kb
Host smart-edb895e0-8f4d-4ea5-a8d4-ca745b094635
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613333839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1613333839
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1196639203
Short name T139
Test name
Test status
Simulation time 47875013 ps
CPU time 1.13 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:26 PM PDT 24
Peak memory 216696 kb
Host smart-1bf1dd24-ca22-4986-b98a-d66fc49eda91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196639203 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1196639203
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2303212944
Short name T126
Test name
Test status
Simulation time 28721635 ps
CPU time 1.19 seconds
Started Jun 07 08:33:14 PM PDT 24
Finished Jun 07 08:33:18 PM PDT 24
Peak memory 220404 kb
Host smart-3249b2ea-1fef-42dd-8e56-592bd92c1294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303212944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2303212944
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3967178295
Short name T604
Test name
Test status
Simulation time 63707773 ps
CPU time 1.48 seconds
Started Jun 07 08:33:01 PM PDT 24
Finished Jun 07 08:33:06 PM PDT 24
Peak memory 219388 kb
Host smart-eff4e850-a795-4446-bd8a-b50b82ca1631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967178295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3967178295
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.1585659850
Short name T438
Test name
Test status
Simulation time 49342774 ps
CPU time 0.94 seconds
Started Jun 07 08:33:03 PM PDT 24
Finished Jun 07 08:33:08 PM PDT 24
Peak memory 215240 kb
Host smart-1a27119c-0461-4c4b-bc5f-2e8a8ae30566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585659850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1585659850
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3850835578
Short name T506
Test name
Test status
Simulation time 248895255 ps
CPU time 1.26 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 216892 kb
Host smart-ea019c38-26f7-4afe-ad4e-ed92fec9aa08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850835578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3850835578
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2726559082
Short name T358
Test name
Test status
Simulation time 78518631855 ps
CPU time 996.03 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:50:03 PM PDT 24
Peak memory 220556 kb
Host smart-60da1c6d-b403-403c-8a48-a5d6c70a6d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726559082 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2726559082
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.607657040
Short name T285
Test name
Test status
Simulation time 266445634 ps
CPU time 1.62 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:12 PM PDT 24
Peak memory 218416 kb
Host smart-0ab18eca-ae2c-4795-97f4-e10de83f17c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607657040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.607657040
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3481036420
Short name T322
Test name
Test status
Simulation time 33380561 ps
CPU time 1.31 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 218068 kb
Host smart-70ff105f-0a20-4d48-a018-ca0c91b38c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481036420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3481036420
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2412777460
Short name T632
Test name
Test status
Simulation time 79788929 ps
CPU time 1.03 seconds
Started Jun 07 08:34:08 PM PDT 24
Finished Jun 07 08:34:14 PM PDT 24
Peak memory 216864 kb
Host smart-0c0c8107-8a12-41b8-953a-e1582c4a5b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412777460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2412777460
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1053484375
Short name T371
Test name
Test status
Simulation time 45895761 ps
CPU time 1.19 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:05 PM PDT 24
Peak memory 216872 kb
Host smart-10b483d2-7fc9-47f1-b259-435e496ee888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053484375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1053484375
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.63127993
Short name T525
Test name
Test status
Simulation time 43709284 ps
CPU time 1.13 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:20 PM PDT 24
Peak memory 216932 kb
Host smart-65e10581-9b82-4989-8dfb-9d43b9785c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63127993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.63127993
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2225157446
Short name T348
Test name
Test status
Simulation time 27921417 ps
CPU time 1.24 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 218160 kb
Host smart-566a4669-9c18-4508-86d7-cac5ebc4965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225157446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2225157446
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1115855662
Short name T421
Test name
Test status
Simulation time 66094621 ps
CPU time 1.16 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:17 PM PDT 24
Peak memory 216860 kb
Host smart-062d419f-76cf-4771-b87a-8e8a4bfed848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115855662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1115855662
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3572415134
Short name T424
Test name
Test status
Simulation time 711540988 ps
CPU time 4.44 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 219356 kb
Host smart-f5d91fc6-4532-4282-999a-3cf7810a6fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572415134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3572415134
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2627406287
Short name T803
Test name
Test status
Simulation time 71389099 ps
CPU time 1.1 seconds
Started Jun 07 08:33:16 PM PDT 24
Finished Jun 07 08:33:20 PM PDT 24
Peak memory 218060 kb
Host smart-967d6dd8-0a33-4e3a-806b-c90b35a8b485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627406287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2627406287
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2538729326
Short name T640
Test name
Test status
Simulation time 38018393 ps
CPU time 0.88 seconds
Started Jun 07 08:33:06 PM PDT 24
Finished Jun 07 08:33:10 PM PDT 24
Peak memory 206264 kb
Host smart-d441fb16-9131-452c-b643-234f7d02fee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538729326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2538729326
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.408519382
Short name T815
Test name
Test status
Simulation time 23493013 ps
CPU time 0.94 seconds
Started Jun 07 08:33:03 PM PDT 24
Finished Jun 07 08:33:07 PM PDT 24
Peak memory 215752 kb
Host smart-1f4a24bc-003c-4fbe-97c1-febf26c40326
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408519382 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.408519382
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.463757454
Short name T492
Test name
Test status
Simulation time 70941943 ps
CPU time 1.1 seconds
Started Jun 07 08:33:04 PM PDT 24
Finished Jun 07 08:33:09 PM PDT 24
Peak memory 218084 kb
Host smart-2cf3c664-7e23-4970-844b-55d777dec25e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463757454 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.463757454
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1229707031
Short name T118
Test name
Test status
Simulation time 39364685 ps
CPU time 1.04 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 229624 kb
Host smart-b3c8a6e1-d380-4b19-946e-40e16dea539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229707031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1229707031
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2010150295
Short name T219
Test name
Test status
Simulation time 200797823 ps
CPU time 1.48 seconds
Started Jun 07 08:33:08 PM PDT 24
Finished Jun 07 08:33:13 PM PDT 24
Peak memory 218332 kb
Host smart-2ac7d8ad-060c-4a2b-aeea-5fbdf78fed00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010150295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2010150295
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1384953074
Short name T543
Test name
Test status
Simulation time 32794215 ps
CPU time 0.88 seconds
Started Jun 07 08:33:17 PM PDT 24
Finished Jun 07 08:33:21 PM PDT 24
Peak memory 215368 kb
Host smart-dd91401b-31aa-438f-b822-578076d49e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384953074 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1384953074
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2631768363
Short name T718
Test name
Test status
Simulation time 52197387 ps
CPU time 0.96 seconds
Started Jun 07 08:33:13 PM PDT 24
Finished Jun 07 08:33:17 PM PDT 24
Peak memory 215236 kb
Host smart-288615f1-d95e-4a86-b4ed-677698121ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631768363 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2631768363
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3888060587
Short name T55
Test name
Test status
Simulation time 174076381 ps
CPU time 4.03 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 215240 kb
Host smart-5b175066-b720-4841-a76d-2032053714d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888060587 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3888060587
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3351508731
Short name T205
Test name
Test status
Simulation time 79910064675 ps
CPU time 504.73 seconds
Started Jun 07 08:32:59 PM PDT 24
Finished Jun 07 08:41:28 PM PDT 24
Peak memory 223572 kb
Host smart-56f71bbc-410b-41ed-897d-43ac5ecce946
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351508731 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3351508731
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.edn_genbits.691807058
Short name T12
Test name
Test status
Simulation time 126442705 ps
CPU time 1.45 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 219592 kb
Host smart-938d8b96-0515-4d7d-b030-008f90c2cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691807058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.691807058
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.266033096
Short name T734
Test name
Test status
Simulation time 30785194 ps
CPU time 1.25 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:17 PM PDT 24
Peak memory 217116 kb
Host smart-352865d6-f1a5-409c-9870-7f05f3a1e569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266033096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.266033096
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2338238710
Short name T317
Test name
Test status
Simulation time 87325049 ps
CPU time 1.36 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 218496 kb
Host smart-55292495-8521-4c9d-9ebd-4c391164b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338238710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2338238710
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1705451255
Short name T372
Test name
Test status
Simulation time 83056672 ps
CPU time 1.68 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:22 PM PDT 24
Peak memory 219648 kb
Host smart-a986ef48-7344-45e6-93d6-67392151eea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705451255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1705451255
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3295894425
Short name T75
Test name
Test status
Simulation time 39204541 ps
CPU time 1.54 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 218060 kb
Host smart-332e8861-9847-4179-b853-75554b1e35da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295894425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3295894425
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.4269694102
Short name T347
Test name
Test status
Simulation time 173370224 ps
CPU time 2.64 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 219748 kb
Host smart-da7407a1-26e7-4909-8cd4-7c36b873de66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269694102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.4269694102
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1347206646
Short name T827
Test name
Test status
Simulation time 199434043 ps
CPU time 2.69 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 217044 kb
Host smart-36529a4f-f778-4e53-a1d6-edf4ea3f226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347206646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1347206646
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.4104615962
Short name T822
Test name
Test status
Simulation time 52108285 ps
CPU time 1.56 seconds
Started Jun 07 08:34:10 PM PDT 24
Finished Jun 07 08:34:17 PM PDT 24
Peak memory 218048 kb
Host smart-7d9fab23-dc2f-44ea-9b24-fd29fe16243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104615962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4104615962
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.3500905397
Short name T66
Test name
Test status
Simulation time 24175194 ps
CPU time 0.9 seconds
Started Jun 07 08:33:15 PM PDT 24
Finished Jun 07 08:33:19 PM PDT 24
Peak memory 206672 kb
Host smart-f1b28c1c-026a-4437-bd3e-ea3c66c764ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500905397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3500905397
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2075953336
Short name T352
Test name
Test status
Simulation time 14879964 ps
CPU time 0.96 seconds
Started Jun 07 08:33:07 PM PDT 24
Finished Jun 07 08:33:11 PM PDT 24
Peak memory 216060 kb
Host smart-05091148-b64a-443d-8549-6c0b62be983e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075953336 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2075953336
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.494117807
Short name T579
Test name
Test status
Simulation time 44657437 ps
CPU time 0.97 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 218028 kb
Host smart-ffecdb6c-fafd-4cd4-a48c-2aa1c2d6124c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494117807 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.494117807
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.793021768
Short name T58
Test name
Test status
Simulation time 119810055 ps
CPU time 1.3 seconds
Started Jun 07 08:33:14 PM PDT 24
Finished Jun 07 08:33:19 PM PDT 24
Peak memory 225652 kb
Host smart-7ba49208-51a5-49cd-a0cd-231de7bf9780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793021768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.793021768
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.4121720988
Short name T455
Test name
Test status
Simulation time 101293265 ps
CPU time 1.37 seconds
Started Jun 07 08:33:16 PM PDT 24
Finished Jun 07 08:33:21 PM PDT 24
Peak memory 218692 kb
Host smart-01fc8714-3df0-40aa-91fe-56a23169b6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121720988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.4121720988
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2863474447
Short name T660
Test name
Test status
Simulation time 20388410 ps
CPU time 1.07 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:24 PM PDT 24
Peak memory 215728 kb
Host smart-b2fa70c3-1371-4da5-a0e2-b529c85b13ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863474447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2863474447
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4004543440
Short name T325
Test name
Test status
Simulation time 29274062 ps
CPU time 0.96 seconds
Started Jun 07 08:33:12 PM PDT 24
Finished Jun 07 08:33:16 PM PDT 24
Peak memory 215188 kb
Host smart-ee66d0fc-ff56-4ae4-96fb-4ea87caf5822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004543440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4004543440
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2798078199
Short name T398
Test name
Test status
Simulation time 315979752 ps
CPU time 5.85 seconds
Started Jun 07 08:33:13 PM PDT 24
Finished Jun 07 08:33:22 PM PDT 24
Peak memory 215184 kb
Host smart-769e740e-1c02-4d04-be6f-0e83574daa31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798078199 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2798078199
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2570070321
Short name T516
Test name
Test status
Simulation time 74778833340 ps
CPU time 1662.34 seconds
Started Jun 07 08:33:11 PM PDT 24
Finished Jun 07 09:00:57 PM PDT 24
Peak memory 224244 kb
Host smart-4d12ac4e-4f6b-4744-b551-2b4cc7031328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570070321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2570070321
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2973729807
Short name T73
Test name
Test status
Simulation time 68437484 ps
CPU time 2.28 seconds
Started Jun 07 08:34:10 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 220004 kb
Host smart-75386f13-3629-458a-a4c6-6b173fef8bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973729807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2973729807
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.366205655
Short name T491
Test name
Test status
Simulation time 42720921 ps
CPU time 1.63 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 217144 kb
Host smart-b970cee3-4ef9-405f-a8eb-acd5b0157bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366205655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.366205655
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1568232810
Short name T723
Test name
Test status
Simulation time 42143640 ps
CPU time 1.69 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:22 PM PDT 24
Peak memory 218084 kb
Host smart-2ea60f5f-6c06-472e-8275-7ca29258bec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568232810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1568232810
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.1579767532
Short name T578
Test name
Test status
Simulation time 49706558 ps
CPU time 1.04 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 217044 kb
Host smart-d9522fa1-48fc-48e6-b396-cc29fd667440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579767532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1579767532
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2381824143
Short name T830
Test name
Test status
Simulation time 282098054 ps
CPU time 2.73 seconds
Started Jun 07 08:34:08 PM PDT 24
Finished Jun 07 08:34:17 PM PDT 24
Peak memory 218736 kb
Host smart-0b45d084-7db4-4812-88a6-8c77d33ad5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381824143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2381824143
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2308321426
Short name T661
Test name
Test status
Simulation time 78473289 ps
CPU time 1.79 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 218464 kb
Host smart-e58ffae1-65b7-40a7-b58e-c8cdeb66cdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308321426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2308321426
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3286027972
Short name T600
Test name
Test status
Simulation time 4321890602 ps
CPU time 85.99 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:35:45 PM PDT 24
Peak memory 218308 kb
Host smart-5faf30a3-4774-4037-92fb-9d0668a84087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286027972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3286027972
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.446593702
Short name T468
Test name
Test status
Simulation time 45461478 ps
CPU time 1.42 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:25 PM PDT 24
Peak memory 218164 kb
Host smart-1f835694-9965-4db9-a586-1d3b62051f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446593702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.446593702
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3766266264
Short name T589
Test name
Test status
Simulation time 62922374 ps
CPU time 1.25 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:25 PM PDT 24
Peak memory 217728 kb
Host smart-0d598690-79cb-4766-887b-6658f2ccded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766266264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3766266264
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.218730845
Short name T515
Test name
Test status
Simulation time 16682568 ps
CPU time 0.96 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:24 PM PDT 24
Peak memory 206520 kb
Host smart-7a53d3ae-987c-43fe-875e-e5082d806f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218730845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.218730845
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1547618240
Short name T201
Test name
Test status
Simulation time 35514530 ps
CPU time 0.85 seconds
Started Jun 07 08:33:10 PM PDT 24
Finished Jun 07 08:33:14 PM PDT 24
Peak memory 215868 kb
Host smart-83b225f3-b052-42e5-b1b0-dacfc5c3a73d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547618240 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1547618240
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.784803857
Short name T112
Test name
Test status
Simulation time 20287676 ps
CPU time 1.03 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 219328 kb
Host smart-56ee8f31-e218-46a2-b756-734e86a3d678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784803857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.784803857
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3827225801
Short name T659
Test name
Test status
Simulation time 152156812 ps
CPU time 3.05 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 219196 kb
Host smart-018b12a9-faed-47c0-a0ca-0025d6db0e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827225801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3827225801
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3906599537
Short name T575
Test name
Test status
Simulation time 42711489 ps
CPU time 0.88 seconds
Started Jun 07 08:33:29 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 215568 kb
Host smart-b4cd893c-5d68-408c-98be-8cc1b45f4f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906599537 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3906599537
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4217385083
Short name T840
Test name
Test status
Simulation time 15831733 ps
CPU time 1.04 seconds
Started Jun 07 08:33:16 PM PDT 24
Finished Jun 07 08:33:21 PM PDT 24
Peak memory 215216 kb
Host smart-b16efb08-6da4-46e7-83e8-dd759e79f041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217385083 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4217385083
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.68526286
Short name T299
Test name
Test status
Simulation time 276336799 ps
CPU time 3.33 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 216552 kb
Host smart-7ca5738f-d0e1-43ea-868d-a1717c9c9c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68526286 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.68526286
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.414342491
Short name T36
Test name
Test status
Simulation time 58335984078 ps
CPU time 1304.71 seconds
Started Jun 07 08:33:12 PM PDT 24
Finished Jun 07 08:54:59 PM PDT 24
Peak memory 220720 kb
Host smart-296bc68e-bbbc-41da-920a-8cd0f9375994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414342491 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.414342491
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3573305386
Short name T315
Test name
Test status
Simulation time 37069901 ps
CPU time 1.38 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 217100 kb
Host smart-5d3ecc79-3fcb-44c4-825f-500d897a824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573305386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3573305386
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.776644539
Short name T824
Test name
Test status
Simulation time 86426557 ps
CPU time 1.72 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 218364 kb
Host smart-1dbc59be-badc-4d01-8b6d-9028ddd7eb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776644539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.776644539
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3029742230
Short name T376
Test name
Test status
Simulation time 62406694 ps
CPU time 1.75 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 218252 kb
Host smart-c0c8bdff-84c0-40f3-a996-2bfd1928f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029742230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3029742230
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3881419253
Short name T637
Test name
Test status
Simulation time 31216879 ps
CPU time 1.01 seconds
Started Jun 07 08:34:10 PM PDT 24
Finished Jun 07 08:34:17 PM PDT 24
Peak memory 215176 kb
Host smart-2c18655d-13bc-4f49-8337-c495af18e110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881419253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3881419253
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.4079579358
Short name T744
Test name
Test status
Simulation time 241391348 ps
CPU time 3.33 seconds
Started Jun 07 08:34:20 PM PDT 24
Finished Jun 07 08:34:33 PM PDT 24
Peak memory 219888 kb
Host smart-5fa93762-6ef1-4dda-b6cb-08908cf17cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079579358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4079579358
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1045123276
Short name T502
Test name
Test status
Simulation time 72868214 ps
CPU time 1.08 seconds
Started Jun 07 08:34:17 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 216896 kb
Host smart-bafcd3a1-d9cd-4835-bdbf-821b3a5eef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045123276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1045123276
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.630733664
Short name T699
Test name
Test status
Simulation time 47474864 ps
CPU time 1.33 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 218240 kb
Host smart-985e4ff8-7ce8-4265-b720-d8b5f7b1d2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630733664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.630733664
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.138097616
Short name T584
Test name
Test status
Simulation time 141568210 ps
CPU time 1.35 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 218596 kb
Host smart-fef5800a-98e7-4d02-ab42-ce7c7162f618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138097616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.138097616
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3886543431
Short name T595
Test name
Test status
Simulation time 30880623 ps
CPU time 1.23 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 216876 kb
Host smart-9861893b-b629-41b9-8a52-0b74715bfc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886543431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3886543431
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.4024552560
Short name T634
Test name
Test status
Simulation time 98362838 ps
CPU time 1.32 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:22 PM PDT 24
Peak memory 218176 kb
Host smart-15d298fa-9893-43e3-b8c6-01625db5bea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024552560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.4024552560
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1044672941
Short name T106
Test name
Test status
Simulation time 31927132 ps
CPU time 1.34 seconds
Started Jun 07 08:33:10 PM PDT 24
Finished Jun 07 08:33:15 PM PDT 24
Peak memory 215704 kb
Host smart-8aa8af87-3e30-4420-a972-9c7e914248a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044672941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1044672941
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1259913865
Short name T764
Test name
Test status
Simulation time 18710280 ps
CPU time 0.98 seconds
Started Jun 07 08:33:11 PM PDT 24
Finished Jun 07 08:33:15 PM PDT 24
Peak memory 214752 kb
Host smart-9db0966b-8e43-44a1-99aa-92d88b509080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259913865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1259913865
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2363226651
Short name T626
Test name
Test status
Simulation time 40849659 ps
CPU time 0.88 seconds
Started Jun 07 08:33:15 PM PDT 24
Finished Jun 07 08:33:18 PM PDT 24
Peak memory 216088 kb
Host smart-07bfd279-f607-4084-b722-7d5495ec9c30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363226651 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2363226651
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3119169738
Short name T495
Test name
Test status
Simulation time 41506917 ps
CPU time 1.28 seconds
Started Jun 07 08:33:16 PM PDT 24
Finished Jun 07 08:33:20 PM PDT 24
Peak memory 219184 kb
Host smart-627db2fd-6614-4b44-820d-5cc091e7fbd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119169738 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3119169738
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.305925963
Short name T810
Test name
Test status
Simulation time 143321219 ps
CPU time 1.19 seconds
Started Jun 07 08:33:07 PM PDT 24
Finished Jun 07 08:33:11 PM PDT 24
Peak memory 219576 kb
Host smart-d87b6483-ebfd-4ac6-b3b4-d6e9c7a15f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305925963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.305925963
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.395009659
Short name T711
Test name
Test status
Simulation time 21936204 ps
CPU time 1.07 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 215528 kb
Host smart-dc8e724d-dbb0-48aa-8f83-aa7714917aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395009659 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.395009659
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.863557552
Short name T583
Test name
Test status
Simulation time 33412835 ps
CPU time 0.87 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 215036 kb
Host smart-d2fa9674-5c7e-4969-acc9-d9ba7ff700d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863557552 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.863557552
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3400546318
Short name T95
Test name
Test status
Simulation time 1202649748 ps
CPU time 4.59 seconds
Started Jun 07 08:33:08 PM PDT 24
Finished Jun 07 08:33:16 PM PDT 24
Peak memory 216808 kb
Host smart-8962d380-2533-40a6-a2ab-6cff2d11700d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400546318 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3400546318
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1871867190
Short name T212
Test name
Test status
Simulation time 471652126889 ps
CPU time 2775.32 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 09:19:39 PM PDT 24
Peak memory 228476 kb
Host smart-1e46f4d4-61ce-4a53-87d1-6d0b7d252b7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871867190 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1871867190
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3993428931
Short name T765
Test name
Test status
Simulation time 59932494 ps
CPU time 1.29 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 218056 kb
Host smart-f78a0ef2-ab1c-4dc6-b07d-08a4b9b9c9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993428931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3993428931
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3953971466
Short name T816
Test name
Test status
Simulation time 171074333 ps
CPU time 1.69 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:25 PM PDT 24
Peak memory 218316 kb
Host smart-9d5916ae-ceaa-4f82-b256-e26a2f81a092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953971466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3953971466
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.236627747
Short name T97
Test name
Test status
Simulation time 48855404 ps
CPU time 1.19 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 218376 kb
Host smart-85a97fc8-db3b-4edb-9267-47dd00d4e5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236627747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.236627747
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.4097128636
Short name T781
Test name
Test status
Simulation time 38947993 ps
CPU time 1.66 seconds
Started Jun 07 08:34:10 PM PDT 24
Finished Jun 07 08:34:17 PM PDT 24
Peak memory 218060 kb
Host smart-d138fac1-a8e3-48b1-8218-1d92b58b3e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097128636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4097128636
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1066800907
Short name T289
Test name
Test status
Simulation time 46050331 ps
CPU time 1.14 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:22 PM PDT 24
Peak memory 218324 kb
Host smart-fff3a75d-a051-4759-a268-1a6efe6ef63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066800907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1066800907
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3765701789
Short name T837
Test name
Test status
Simulation time 39305415 ps
CPU time 1.15 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 219116 kb
Host smart-fe567a94-d6f3-4867-be1f-7ca5de023b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765701789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3765701789
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1285362451
Short name T686
Test name
Test status
Simulation time 46870356 ps
CPU time 1.58 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 219568 kb
Host smart-22f2100c-6da5-4b09-bec1-327b49d946c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285362451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1285362451
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1698877056
Short name T521
Test name
Test status
Simulation time 33729298 ps
CPU time 1.26 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 216852 kb
Host smart-88a993ee-a447-4fb3-b6d7-022baa7ffada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698877056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1698877056
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1942740033
Short name T280
Test name
Test status
Simulation time 44500225 ps
CPU time 1.43 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 217676 kb
Host smart-e4fc1e34-8624-4f3e-9afb-02cc6371ce86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942740033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1942740033
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3351933311
Short name T763
Test name
Test status
Simulation time 115629667 ps
CPU time 1.31 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:22 PM PDT 24
Peak memory 218448 kb
Host smart-904e535a-3463-4c18-a9c3-d0f234851a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351933311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3351933311
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2938026655
Short name T121
Test name
Test status
Simulation time 43447676 ps
CPU time 1.16 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 219220 kb
Host smart-f9ba5c10-bda6-457b-8e9c-4f9839700d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938026655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2938026655
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1530666777
Short name T691
Test name
Test status
Simulation time 75264734 ps
CPU time 1.02 seconds
Started Jun 07 08:33:17 PM PDT 24
Finished Jun 07 08:33:22 PM PDT 24
Peak memory 214804 kb
Host smart-b8949ab6-d731-43b0-9846-9c08032fc520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530666777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1530666777
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1551156428
Short name T548
Test name
Test status
Simulation time 13178208 ps
CPU time 0.92 seconds
Started Jun 07 08:33:08 PM PDT 24
Finished Jun 07 08:33:12 PM PDT 24
Peak memory 216132 kb
Host smart-6eefd81c-1b6e-41a0-9655-b7cb0f22e845
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551156428 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1551156428
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.594313095
Short name T499
Test name
Test status
Simulation time 24602077 ps
CPU time 1.07 seconds
Started Jun 07 08:33:10 PM PDT 24
Finished Jun 07 08:33:14 PM PDT 24
Peak memory 216748 kb
Host smart-5dca8c22-3411-46f5-9679-9f0ee9401d9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594313095 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.594313095
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2050814643
Short name T124
Test name
Test status
Simulation time 20946521 ps
CPU time 1.26 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:23 PM PDT 24
Peak memory 229632 kb
Host smart-3bd1ef91-7a7b-422c-8606-318433bcdcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050814643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2050814643
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3061309280
Short name T382
Test name
Test status
Simulation time 92315768 ps
CPU time 1.4 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 218480 kb
Host smart-7d128b0e-0cf5-4e0d-b505-c9f8ed0e5238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061309280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3061309280
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2653307957
Short name T758
Test name
Test status
Simulation time 26537523 ps
CPU time 0.96 seconds
Started Jun 07 08:33:14 PM PDT 24
Finished Jun 07 08:33:18 PM PDT 24
Peak memory 215752 kb
Host smart-f4e28c15-fdd6-4b5c-990d-8aa950322bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653307957 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2653307957
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2399789519
Short name T414
Test name
Test status
Simulation time 14531465 ps
CPU time 0.91 seconds
Started Jun 07 08:33:12 PM PDT 24
Finished Jun 07 08:33:16 PM PDT 24
Peak memory 215236 kb
Host smart-460351f3-315d-4617-9b14-68881678787f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399789519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2399789519
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3138138423
Short name T497
Test name
Test status
Simulation time 456779996 ps
CPU time 3.12 seconds
Started Jun 07 08:33:05 PM PDT 24
Finished Jun 07 08:33:12 PM PDT 24
Peak memory 216844 kb
Host smart-d948fa87-45d0-44f6-9796-7e91f7ab08c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138138423 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3138138423
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2241753204
Short name T549
Test name
Test status
Simulation time 115170880750 ps
CPU time 931.81 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:49:04 PM PDT 24
Peak memory 223568 kb
Host smart-90ea9455-1c0d-4d05-bc32-903e21bd30b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241753204 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2241753204
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.3090864301
Short name T345
Test name
Test status
Simulation time 55111400 ps
CPU time 1.01 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:30 PM PDT 24
Peak memory 216968 kb
Host smart-b299119f-e241-4ba6-9a8f-bb1c449f1c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090864301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3090864301
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.269880615
Short name T588
Test name
Test status
Simulation time 97624886 ps
CPU time 1.13 seconds
Started Jun 07 08:34:17 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 217024 kb
Host smart-b5543f1b-fec6-4152-ae87-e9e2cd86a499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269880615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.269880615
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.27679462
Short name T582
Test name
Test status
Simulation time 53799835 ps
CPU time 1.22 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:25 PM PDT 24
Peak memory 218020 kb
Host smart-948c8101-bbfd-4015-9f82-f4a9d678b6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27679462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.27679462
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.236800561
Short name T476
Test name
Test status
Simulation time 38943953 ps
CPU time 1.69 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 218144 kb
Host smart-52e5f40f-52cc-40a5-b45b-2ea38f7dc16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236800561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.236800561
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2442970115
Short name T713
Test name
Test status
Simulation time 49832579 ps
CPU time 1.08 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:25 PM PDT 24
Peak memory 218212 kb
Host smart-ed2e9e81-19b5-4f48-96d8-dbc9ff9a39d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442970115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2442970115
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3278464170
Short name T437
Test name
Test status
Simulation time 39507805 ps
CPU time 1.47 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 217032 kb
Host smart-248bbfb0-1462-4465-84d6-db42ce7a09b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278464170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3278464170
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3938015975
Short name T63
Test name
Test status
Simulation time 23196278 ps
CPU time 1.05 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 216812 kb
Host smart-3c3c09fe-36b0-41b5-9e1d-3c30dbd2ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938015975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3938015975
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.935807222
Short name T48
Test name
Test status
Simulation time 65878910 ps
CPU time 1.52 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:24 PM PDT 24
Peak memory 218100 kb
Host smart-f6999f8a-a50e-485f-ba17-565391ba307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935807222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.935807222
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.989112426
Short name T11
Test name
Test status
Simulation time 75190560 ps
CPU time 1.13 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 219460 kb
Host smart-d79b792c-a128-4c27-8074-6a7e4c6c664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989112426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.989112426
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1903867798
Short name T638
Test name
Test status
Simulation time 38749547 ps
CPU time 1.46 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 218280 kb
Host smart-afdfe342-2f41-4a74-970b-7d0d574789db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903867798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1903867798
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3638863065
Short name T107
Test name
Test status
Simulation time 79438765 ps
CPU time 1 seconds
Started Jun 07 08:32:44 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 219136 kb
Host smart-eedede67-3916-46cd-b440-decd4dda6033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638863065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3638863065
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3111583569
Short name T400
Test name
Test status
Simulation time 17392083 ps
CPU time 0.93 seconds
Started Jun 07 08:32:39 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 214724 kb
Host smart-afb335f4-87e5-4a3d-9814-8d62eaa19582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111583569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3111583569
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3422454010
Short name T197
Test name
Test status
Simulation time 21453327 ps
CPU time 0.84 seconds
Started Jun 07 08:32:39 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 216144 kb
Host smart-a12a132b-3995-4511-8f03-41db06a07973
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422454010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3422454010
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.98465485
Short name T350
Test name
Test status
Simulation time 57366696 ps
CPU time 0.94 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 218160 kb
Host smart-6ec318b6-8c3b-4e83-8440-adbc46af7f34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98465485 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disa
ble_auto_req_mode.98465485
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1654282243
Short name T15
Test name
Test status
Simulation time 20340752 ps
CPU time 1.15 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 224012 kb
Host smart-8ae0c5cb-a054-48dc-99bf-b1c2a462d63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654282243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1654282243
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.682228045
Short name T389
Test name
Test status
Simulation time 108927616 ps
CPU time 1.29 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 216804 kb
Host smart-0c8fbbc3-582c-4410-9026-2cc7ab34f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682228045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.682228045
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2322044452
Short name T693
Test name
Test status
Simulation time 24575495 ps
CPU time 0.91 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 215740 kb
Host smart-88afcdcf-93d9-4f05-8be0-0a7f0593f4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322044452 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2322044452
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2314707830
Short name T16
Test name
Test status
Simulation time 245344025 ps
CPU time 4.09 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 235376 kb
Host smart-8c9bbab7-2d6c-4efd-a03b-973af8822c0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314707830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2314707830
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2333709900
Short name T599
Test name
Test status
Simulation time 48173451 ps
CPU time 0.96 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 215184 kb
Host smart-b15684e0-dbdc-495f-bb97-ea8e5c94d5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333709900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2333709900
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3437245337
Short name T523
Test name
Test status
Simulation time 60456838 ps
CPU time 1.8 seconds
Started Jun 07 08:32:44 PM PDT 24
Finished Jun 07 08:32:54 PM PDT 24
Peak memory 215296 kb
Host smart-cbf6b0f2-557e-48f9-a08f-a9bbf8406800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437245337 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3437245337
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.956707319
Short name T211
Test name
Test status
Simulation time 72326792527 ps
CPU time 414.72 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:39:55 PM PDT 24
Peak memory 223708 kb
Host smart-5762d60f-371e-4a82-8b56-cc18326cbcee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956707319 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.956707319
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3446708856
Short name T50
Test name
Test status
Simulation time 46287721 ps
CPU time 1.28 seconds
Started Jun 07 08:33:12 PM PDT 24
Finished Jun 07 08:33:16 PM PDT 24
Peak memory 219960 kb
Host smart-65b2a46b-4f7c-46bb-a533-54f9bb870733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446708856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3446708856
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3137117678
Short name T334
Test name
Test status
Simulation time 20117290 ps
CPU time 0.9 seconds
Started Jun 07 08:33:17 PM PDT 24
Finished Jun 07 08:33:22 PM PDT 24
Peak memory 206512 kb
Host smart-977ffc5c-76c4-425b-8095-c33c161b2fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137117678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3137117678
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1785469260
Short name T203
Test name
Test status
Simulation time 39039602 ps
CPU time 0.84 seconds
Started Jun 07 08:33:09 PM PDT 24
Finished Jun 07 08:33:12 PM PDT 24
Peak memory 215256 kb
Host smart-dca13905-f858-42e1-871d-68e65991b01e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785469260 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1785469260
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.210541184
Short name T806
Test name
Test status
Simulation time 44185714 ps
CPU time 1.3 seconds
Started Jun 07 08:33:15 PM PDT 24
Finished Jun 07 08:33:19 PM PDT 24
Peak memory 218116 kb
Host smart-fbc31ac3-43af-4cdd-88e9-f1c540fc1375
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210541184 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.210541184
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1838219972
Short name T127
Test name
Test status
Simulation time 126321919 ps
CPU time 1.14 seconds
Started Jun 07 08:33:04 PM PDT 24
Finished Jun 07 08:33:09 PM PDT 24
Peak memory 228580 kb
Host smart-78056cae-5c36-4fbd-a874-6d2038d1f824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838219972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1838219972
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3539221234
Short name T17
Test name
Test status
Simulation time 30046927 ps
CPU time 1.29 seconds
Started Jun 07 08:33:07 PM PDT 24
Finished Jun 07 08:33:12 PM PDT 24
Peak memory 219384 kb
Host smart-e825df38-6e18-4ff2-9a66-490fd3b0643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539221234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3539221234
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2529569116
Short name T87
Test name
Test status
Simulation time 21952876 ps
CPU time 1.08 seconds
Started Jun 07 08:33:16 PM PDT 24
Finished Jun 07 08:33:20 PM PDT 24
Peak memory 215892 kb
Host smart-3848a842-cf0e-413b-86b1-f82909280dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529569116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2529569116
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.48275185
Short name T259
Test name
Test status
Simulation time 30795343 ps
CPU time 1.03 seconds
Started Jun 07 08:33:10 PM PDT 24
Finished Jun 07 08:33:14 PM PDT 24
Peak memory 214960 kb
Host smart-207df874-d0cb-498d-835d-2e7aac88df81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48275185 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.48275185
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.4173194347
Short name T366
Test name
Test status
Simulation time 339610215 ps
CPU time 6.6 seconds
Started Jun 07 08:33:15 PM PDT 24
Finished Jun 07 08:33:24 PM PDT 24
Peak memory 215252 kb
Host smart-e1b0edef-0b74-4785-a2f4-d880fc4048a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173194347 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.4173194347
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.4050009649
Short name T706
Test name
Test status
Simulation time 28093450892 ps
CPU time 617.03 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:43:48 PM PDT 24
Peak memory 218896 kb
Host smart-bc11e200-6220-4a09-9c1d-7178952d3548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050009649 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.4050009649
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2473216618
Short name T406
Test name
Test status
Simulation time 128370357 ps
CPU time 1.06 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 216952 kb
Host smart-c334b241-9b6a-486e-8815-491bd837ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473216618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2473216618
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3187990748
Short name T721
Test name
Test status
Simulation time 71848226 ps
CPU time 1.52 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 218560 kb
Host smart-805fd1bd-37f7-4f1e-89b6-679790d134d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187990748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3187990748
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2030295021
Short name T605
Test name
Test status
Simulation time 55608068 ps
CPU time 1.22 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 217856 kb
Host smart-abe0cfcc-0cbb-45fa-aeb4-2d2fa7867477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030295021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2030295021
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3009855364
Short name T778
Test name
Test status
Simulation time 73515947 ps
CPU time 1.14 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 216976 kb
Host smart-2518eaac-2fcd-4396-8762-c6449c2f04e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009855364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3009855364
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2588632361
Short name T412
Test name
Test status
Simulation time 75382262 ps
CPU time 1.06 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 217224 kb
Host smart-8a1ce102-65d2-4b1f-8fee-d99e2c6099dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588632361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2588632361
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1531979402
Short name T673
Test name
Test status
Simulation time 150715487 ps
CPU time 1.73 seconds
Started Jun 07 08:34:24 PM PDT 24
Finished Jun 07 08:34:36 PM PDT 24
Peak memory 218452 kb
Host smart-cb6bf7a9-d15b-4238-991b-700bf4dc42aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531979402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1531979402
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3641096976
Short name T473
Test name
Test status
Simulation time 228418752 ps
CPU time 3.29 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:25 PM PDT 24
Peak memory 218576 kb
Host smart-27a55166-6377-4689-85da-e7554238cc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641096976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3641096976
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.97949354
Short name T431
Test name
Test status
Simulation time 277035215 ps
CPU time 3.18 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 218268 kb
Host smart-e70cbfa8-6f80-429e-a877-a33acd7ed889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97949354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.97949354
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.197731773
Short name T518
Test name
Test status
Simulation time 44996797 ps
CPU time 1 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 216984 kb
Host smart-aae1c20f-63c6-447f-9229-0baeae68685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197731773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.197731773
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3975221383
Short name T161
Test name
Test status
Simulation time 52921676 ps
CPU time 1.02 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 218028 kb
Host smart-54c24407-aac7-40c9-98c0-916a1bedf537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975221383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3975221383
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3995948561
Short name T652
Test name
Test status
Simulation time 23525736 ps
CPU time 0.9 seconds
Started Jun 07 08:33:15 PM PDT 24
Finished Jun 07 08:33:19 PM PDT 24
Peak memory 206584 kb
Host smart-05a5aa23-9aa1-4dfd-843c-faac1c18eae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995948561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3995948561
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3943670976
Short name T459
Test name
Test status
Simulation time 35190374 ps
CPU time 0.91 seconds
Started Jun 07 08:33:12 PM PDT 24
Finished Jun 07 08:33:16 PM PDT 24
Peak memory 216096 kb
Host smart-52c006b2-636b-4dc1-9f58-a92bfe62c676
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943670976 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3943670976
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3870468845
Short name T787
Test name
Test status
Simulation time 32575359 ps
CPU time 1.24 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:26 PM PDT 24
Peak memory 216684 kb
Host smart-c5a5ce82-a734-448b-9f2c-1e765a7383fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870468845 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3870468845
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3534892400
Short name T355
Test name
Test status
Simulation time 19904644 ps
CPU time 1.11 seconds
Started Jun 07 08:33:13 PM PDT 24
Finished Jun 07 08:33:17 PM PDT 24
Peak memory 218468 kb
Host smart-27cc51df-4b4a-404b-ac10-60ecb18fc7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534892400 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3534892400
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.169727997
Short name T85
Test name
Test status
Simulation time 69632496 ps
CPU time 2.64 seconds
Started Jun 07 08:33:14 PM PDT 24
Finished Jun 07 08:33:19 PM PDT 24
Peak memory 215312 kb
Host smart-a4f2bbb9-31be-4cd1-865c-0ab39ff66576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169727997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.169727997
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1092114038
Short name T446
Test name
Test status
Simulation time 92200630 ps
CPU time 0.89 seconds
Started Jun 07 08:33:16 PM PDT 24
Finished Jun 07 08:33:21 PM PDT 24
Peak memory 223832 kb
Host smart-e5e72531-35b2-4c3e-8794-56d5e338fab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092114038 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1092114038
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.418396757
Short name T834
Test name
Test status
Simulation time 53863414 ps
CPU time 0.94 seconds
Started Jun 07 08:33:13 PM PDT 24
Finished Jun 07 08:33:17 PM PDT 24
Peak memory 207028 kb
Host smart-b72b7644-acb3-442a-b7ce-656c0b6d2fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418396757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.418396757
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1038935238
Short name T628
Test name
Test status
Simulation time 413928764 ps
CPU time 2.48 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 215224 kb
Host smart-04653f1a-6af0-476c-a029-258a4da768a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038935238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1038935238
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2049766553
Short name T772
Test name
Test status
Simulation time 14099044196 ps
CPU time 352.74 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:39:21 PM PDT 24
Peak memory 223332 kb
Host smart-aa949ab8-b021-404b-9cdb-54d8ea927dae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049766553 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2049766553
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/211.edn_genbits.2943101825
Short name T753
Test name
Test status
Simulation time 100993843 ps
CPU time 1.35 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 218652 kb
Host smart-1afd2d5a-289f-4c48-86f6-77ace3849377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943101825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2943101825
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1882076205
Short name T629
Test name
Test status
Simulation time 53018054 ps
CPU time 1.51 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 218272 kb
Host smart-4a865c1d-7fbc-4784-9992-c2c2f40a7b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882076205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1882076205
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2629611425
Short name T466
Test name
Test status
Simulation time 51367880 ps
CPU time 1.01 seconds
Started Jun 07 08:34:12 PM PDT 24
Finished Jun 07 08:34:19 PM PDT 24
Peak memory 216972 kb
Host smart-2554f11b-e87c-4953-8029-83075d950b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629611425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2629611425
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.81843887
Short name T702
Test name
Test status
Simulation time 39375953 ps
CPU time 1.39 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:31 PM PDT 24
Peak memory 218084 kb
Host smart-79ba2e8c-624c-4148-acef-2cf642f1996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81843887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.81843887
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1354127078
Short name T286
Test name
Test status
Simulation time 42746236 ps
CPU time 1.2 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 218308 kb
Host smart-df1c1804-fb72-41e3-8038-d8c1c3d63a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354127078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1354127078
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3331762132
Short name T685
Test name
Test status
Simulation time 56858774 ps
CPU time 1.18 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:34:32 PM PDT 24
Peak memory 218172 kb
Host smart-443b92a2-0be0-43e9-b526-1ba883602c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331762132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3331762132
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3963336211
Short name T451
Test name
Test status
Simulation time 44190552 ps
CPU time 1.21 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 216932 kb
Host smart-dce72661-8803-448d-a0b1-3ef441c098de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963336211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3963336211
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3703264941
Short name T314
Test name
Test status
Simulation time 30920855 ps
CPU time 1.28 seconds
Started Jun 07 08:34:17 PM PDT 24
Finished Jun 07 08:34:28 PM PDT 24
Peak memory 218372 kb
Host smart-7f102009-cd27-4817-8941-a2767acbe19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703264941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3703264941
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.266206381
Short name T732
Test name
Test status
Simulation time 34414741 ps
CPU time 1.45 seconds
Started Jun 07 08:34:17 PM PDT 24
Finished Jun 07 08:34:28 PM PDT 24
Peak memory 218260 kb
Host smart-987a18f8-bc86-41b6-a188-379b05782ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266206381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.266206381
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.3853784525
Short name T738
Test name
Test status
Simulation time 12551158 ps
CPU time 0.92 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:24 PM PDT 24
Peak memory 206928 kb
Host smart-31bee9d5-0d23-494c-abf6-4ad49735c554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853784525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3853784525
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3465911757
Short name T598
Test name
Test status
Simulation time 19483432 ps
CPU time 0.9 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 215336 kb
Host smart-bfc4630a-8b04-49f9-b257-627b0b56df69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465911757 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3465911757
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3507360033
Short name T704
Test name
Test status
Simulation time 31455004 ps
CPU time 1.24 seconds
Started Jun 07 08:33:16 PM PDT 24
Finished Jun 07 08:33:21 PM PDT 24
Peak memory 219468 kb
Host smart-db40aff1-3fbd-4903-ae55-8f4511ef44f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507360033 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3507360033
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2454579238
Short name T819
Test name
Test status
Simulation time 46743931 ps
CPU time 0.87 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:25 PM PDT 24
Peak memory 218452 kb
Host smart-d279e21e-8cb4-47e5-a72a-5d3f5e6bc334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454579238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2454579238
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3919308583
Short name T514
Test name
Test status
Simulation time 46176031 ps
CPU time 1.23 seconds
Started Jun 07 08:33:17 PM PDT 24
Finished Jun 07 08:33:22 PM PDT 24
Peak memory 216928 kb
Host smart-5bc91a07-ce07-4f57-aa31-007ccabe25e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919308583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3919308583
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3093734298
Short name T761
Test name
Test status
Simulation time 26122427 ps
CPU time 0.95 seconds
Started Jun 07 08:33:17 PM PDT 24
Finished Jun 07 08:33:23 PM PDT 24
Peak memory 215784 kb
Host smart-42d8d73e-fa74-4eb5-b978-6f76a6e9da3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093734298 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3093734298
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4271213599
Short name T328
Test name
Test status
Simulation time 26436354 ps
CPU time 0.92 seconds
Started Jun 07 08:33:15 PM PDT 24
Finished Jun 07 08:33:19 PM PDT 24
Peak memory 215216 kb
Host smart-ae428f0a-38bc-4161-afcb-78145569e808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271213599 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4271213599
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.406274580
Short name T404
Test name
Test status
Simulation time 2518747239 ps
CPU time 4.25 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 216768 kb
Host smart-77a02bf3-02e8-4276-9bc9-d7e70c647fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406274580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.406274580
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3293121151
Short name T207
Test name
Test status
Simulation time 29367420313 ps
CPU time 744.76 seconds
Started Jun 07 08:33:11 PM PDT 24
Finished Jun 07 08:45:39 PM PDT 24
Peak memory 218528 kb
Host smart-ffbc47e7-8048-46e1-91db-f78f918c2836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293121151 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3293121151
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3183108192
Short name T357
Test name
Test status
Simulation time 146694110 ps
CPU time 1.53 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:24 PM PDT 24
Peak memory 219824 kb
Host smart-49d48db5-ec6e-4c4b-9d3e-1e47a152d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183108192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3183108192
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1729109846
Short name T558
Test name
Test status
Simulation time 117445062 ps
CPU time 1.37 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:24 PM PDT 24
Peak memory 217312 kb
Host smart-acf6e625-a4af-48d3-9326-ede2830b8a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729109846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1729109846
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2364703571
Short name T480
Test name
Test status
Simulation time 82934192 ps
CPU time 1.39 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 219584 kb
Host smart-907b69e4-f788-4e1f-b5b3-7ce665e8c0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364703571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2364703571
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.295453792
Short name T560
Test name
Test status
Simulation time 214549200 ps
CPU time 1.42 seconds
Started Jun 07 08:34:17 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 218536 kb
Host smart-62392738-96f9-4b17-9230-c67e94b6e93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295453792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.295453792
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2792679701
Short name T349
Test name
Test status
Simulation time 27268411 ps
CPU time 1.23 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 219428 kb
Host smart-2d072794-c098-4c04-bc16-8e365e277283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792679701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2792679701
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1453188828
Short name T846
Test name
Test status
Simulation time 56339742 ps
CPU time 1.18 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 216860 kb
Host smart-026f85ae-07e7-4ae1-b56a-e96ef9ccf06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453188828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1453188828
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2992075967
Short name T308
Test name
Test status
Simulation time 45537752 ps
CPU time 1.23 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 218044 kb
Host smart-eb59b04f-5e87-47d3-9a56-5bc7c53b4992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992075967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2992075967
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3620482753
Short name T457
Test name
Test status
Simulation time 51994680 ps
CPU time 1.24 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 217020 kb
Host smart-edbf764b-0e96-4125-8c58-1f44f574a29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620482753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3620482753
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.7500732
Short name T641
Test name
Test status
Simulation time 141627242 ps
CPU time 1.1 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:28 PM PDT 24
Peak memory 216944 kb
Host smart-115731b1-06e8-4cf0-bd71-d2149d6ddf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7500732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.7500732
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1311785023
Short name T217
Test name
Test status
Simulation time 44180845 ps
CPU time 1.11 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:34:32 PM PDT 24
Peak memory 216928 kb
Host smart-d7f0a92e-eb30-4957-8ce8-91d8200fb6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311785023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1311785023
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2087509774
Short name T150
Test name
Test status
Simulation time 24594390 ps
CPU time 1.2 seconds
Started Jun 07 08:33:17 PM PDT 24
Finished Jun 07 08:33:22 PM PDT 24
Peak memory 220436 kb
Host smart-29b616da-16e1-45e4-a8ce-31046e5ecf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087509774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2087509774
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2906154909
Short name T53
Test name
Test status
Simulation time 23986171 ps
CPU time 0.88 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:24 PM PDT 24
Peak memory 206552 kb
Host smart-46025ec0-8746-42ba-aa8d-b2c903671aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906154909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2906154909
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.4065622864
Short name T198
Test name
Test status
Simulation time 20572976 ps
CPU time 0.85 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 216160 kb
Host smart-41218084-47ab-4c27-8f2b-cd745a3919d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065622864 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.4065622864
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.882330675
Short name T354
Test name
Test status
Simulation time 66190800 ps
CPU time 1.03 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 216604 kb
Host smart-4c6fe896-15c3-42ff-b84c-775e6a721b33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882330675 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.882330675
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3014608132
Short name T148
Test name
Test status
Simulation time 116067090 ps
CPU time 1 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 219816 kb
Host smart-6842ab2a-c943-48a2-8a88-1416ea89496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014608132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3014608132
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2190084708
Short name T288
Test name
Test status
Simulation time 128779089 ps
CPU time 1.17 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 219112 kb
Host smart-fe6c6431-0b5a-407f-91d6-9050c0c33766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190084708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2190084708
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.933992086
Short name T644
Test name
Test status
Simulation time 109689126 ps
CPU time 0.98 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 223796 kb
Host smart-d35f8943-f752-4e36-9413-9f8dc698b165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933992086 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.933992086
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.4196340169
Short name T330
Test name
Test status
Simulation time 45244992 ps
CPU time 0.89 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 215152 kb
Host smart-b9792dca-38eb-4d4b-b4b4-99570531d826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196340169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.4196340169
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.327814774
Short name T304
Test name
Test status
Simulation time 561815341 ps
CPU time 3.32 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 217088 kb
Host smart-88292901-f704-4297-a385-d7290dee4055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327814774 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.327814774
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1948876224
Short name T434
Test name
Test status
Simulation time 86825367651 ps
CPU time 548.63 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:42:34 PM PDT 24
Peak memory 220076 kb
Host smart-547d87d7-62ac-4989-a791-c06c2d1f0df6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948876224 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1948876224
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.218407409
Short name T648
Test name
Test status
Simulation time 72228250 ps
CPU time 1.13 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:30 PM PDT 24
Peak memory 218616 kb
Host smart-7ea4f4fd-25ab-40bd-9136-fe8465b057e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218407409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.218407409
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1834881275
Short name T319
Test name
Test status
Simulation time 43448562 ps
CPU time 1.36 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 217248 kb
Host smart-aa7b6bd1-60cc-4cc2-801f-252b56279650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834881275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1834881275
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3422885195
Short name T83
Test name
Test status
Simulation time 153482926 ps
CPU time 3.18 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:36 PM PDT 24
Peak memory 219964 kb
Host smart-410264b5-87b5-44cc-b7bf-16443c464aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422885195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3422885195
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.256467440
Short name T410
Test name
Test status
Simulation time 32145812 ps
CPU time 1.35 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 217996 kb
Host smart-347ad650-eec2-4119-87f7-784cf8c2d758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256467440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.256467440
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.113840377
Short name T754
Test name
Test status
Simulation time 43745457 ps
CPU time 1.14 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 215128 kb
Host smart-4a44a898-4081-4ee2-8f63-b456d490acb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113840377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.113840377
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2674361215
Short name T777
Test name
Test status
Simulation time 26200427 ps
CPU time 1.19 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:34:32 PM PDT 24
Peak memory 219336 kb
Host smart-ad8012bf-f1d5-4d60-b50f-302dc000c827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674361215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2674361215
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.344681316
Short name T843
Test name
Test status
Simulation time 87305519 ps
CPU time 1.52 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:25 PM PDT 24
Peak memory 218372 kb
Host smart-00a8e468-fbf7-4c9d-b85f-550fa7d8ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344681316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.344681316
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2780474719
Short name T80
Test name
Test status
Simulation time 80143628 ps
CPU time 1.08 seconds
Started Jun 07 08:34:20 PM PDT 24
Finished Jun 07 08:34:31 PM PDT 24
Peak memory 216968 kb
Host smart-e74d1f53-1439-474d-a715-8a07d914b87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780474719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2780474719
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3534813684
Short name T305
Test name
Test status
Simulation time 255795090 ps
CPU time 3.72 seconds
Started Jun 07 08:34:20 PM PDT 24
Finished Jun 07 08:34:34 PM PDT 24
Peak memory 218188 kb
Host smart-9d3c7c18-ff18-49cf-90a7-30bb49b583ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534813684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3534813684
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3703594602
Short name T646
Test name
Test status
Simulation time 62881302 ps
CPU time 1.38 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 218120 kb
Host smart-ddf51af9-80a9-480e-8fdb-aba2b3fa3313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703594602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3703594602
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.404566808
Short name T172
Test name
Test status
Simulation time 23770482 ps
CPU time 1.15 seconds
Started Jun 07 08:33:29 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 219332 kb
Host smart-2270584d-bae9-4da9-a588-f023228b234b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404566808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.404566808
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2745964228
Short name T845
Test name
Test status
Simulation time 57047033 ps
CPU time 0.96 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 214684 kb
Host smart-2253c7cf-fbde-42dd-ab4c-f8dc6d8023d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745964228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2745964228
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1341391486
Short name T736
Test name
Test status
Simulation time 56865626 ps
CPU time 0.83 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:23 PM PDT 24
Peak memory 215832 kb
Host smart-cf314911-a607-409f-9abe-3de3bee4c694
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341391486 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1341391486
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.903147047
Short name T551
Test name
Test status
Simulation time 63337797 ps
CPU time 1.18 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 216784 kb
Host smart-e9a8fc3e-b1e9-40b0-8f03-8f5c82ba6186
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903147047 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.903147047
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1819869645
Short name T114
Test name
Test status
Simulation time 24486669 ps
CPU time 1.27 seconds
Started Jun 07 08:33:17 PM PDT 24
Finished Jun 07 08:33:23 PM PDT 24
Peak memory 229692 kb
Host smart-734727b5-4cdc-4e59-8823-9a54caaac156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819869645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1819869645
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3651776711
Short name T323
Test name
Test status
Simulation time 74894518 ps
CPU time 1.29 seconds
Started Jun 07 08:33:11 PM PDT 24
Finished Jun 07 08:33:16 PM PDT 24
Peak memory 218232 kb
Host smart-db41dac3-c814-4cb5-af04-dfd90dafe9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651776711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3651776711
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2802486682
Short name T111
Test name
Test status
Simulation time 36245601 ps
CPU time 0.88 seconds
Started Jun 07 08:33:15 PM PDT 24
Finished Jun 07 08:33:19 PM PDT 24
Peak memory 215556 kb
Host smart-76c30380-ed54-4c22-990d-61f192a629af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802486682 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2802486682
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.14117498
Short name T707
Test name
Test status
Simulation time 25338011 ps
CPU time 0.99 seconds
Started Jun 07 08:33:10 PM PDT 24
Finished Jun 07 08:33:13 PM PDT 24
Peak memory 215204 kb
Host smart-b61ac84b-aab1-41f4-a888-439de5d540d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14117498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.14117498
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.112243485
Short name T731
Test name
Test status
Simulation time 247973049 ps
CPU time 5.08 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 215240 kb
Host smart-bcb24ee9-0b08-4254-bd83-b5347a996609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112243485 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.112243485
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3350846075
Short name T794
Test name
Test status
Simulation time 295918793828 ps
CPU time 1332.9 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:55:43 PM PDT 24
Peak memory 223780 kb
Host smart-e3777969-1ec5-44a6-b518-e2b970d32442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350846075 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3350846075
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.720095007
Short name T667
Test name
Test status
Simulation time 65339286 ps
CPU time 2.37 seconds
Started Jun 07 08:34:42 PM PDT 24
Finished Jun 07 08:34:49 PM PDT 24
Peak memory 218228 kb
Host smart-3c3e85a8-d10c-439e-8b2c-35c60ddbac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720095007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.720095007
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3649949946
Short name T818
Test name
Test status
Simulation time 32593693 ps
CPU time 1.44 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 218216 kb
Host smart-6417074f-5ca6-416b-9c0e-9d32bf82dad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649949946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3649949946
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1890441004
Short name T487
Test name
Test status
Simulation time 24844332 ps
CPU time 1.11 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:30 PM PDT 24
Peak memory 216872 kb
Host smart-13cd76dc-6e77-4f34-8966-bc063bc8fd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890441004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1890441004
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.4200727175
Short name T805
Test name
Test status
Simulation time 58762389 ps
CPU time 1.35 seconds
Started Jun 07 08:34:16 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 219316 kb
Host smart-c3051297-449d-4a8b-b934-0cb30dee3557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200727175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4200727175
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1375220337
Short name T531
Test name
Test status
Simulation time 63827274 ps
CPU time 1.18 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 218328 kb
Host smart-50f2491b-1149-45a1-a380-98ce0162a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375220337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1375220337
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2029805934
Short name T585
Test name
Test status
Simulation time 49010325 ps
CPU time 1.18 seconds
Started Jun 07 08:34:23 PM PDT 24
Finished Jun 07 08:34:34 PM PDT 24
Peak memory 216956 kb
Host smart-92c7f089-4d94-4996-b8af-e0b96e79142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029805934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2029805934
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2450677790
Short name T39
Test name
Test status
Simulation time 258683660 ps
CPU time 1.44 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:22 PM PDT 24
Peak memory 218816 kb
Host smart-bfd5f0df-6066-4564-8f34-0f5129effdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450677790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2450677790
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2124226245
Short name T636
Test name
Test status
Simulation time 48343889 ps
CPU time 1.44 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 216892 kb
Host smart-9fa136e6-5400-416c-99d1-486f7235cb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124226245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2124226245
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2589539551
Short name T617
Test name
Test status
Simulation time 80005241 ps
CPU time 1.22 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:34:33 PM PDT 24
Peak memory 218668 kb
Host smart-8c17fb62-589f-4f70-bb1b-5d4e5eec191d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589539551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2589539551
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.725645835
Short name T720
Test name
Test status
Simulation time 108765194 ps
CPU time 1.55 seconds
Started Jun 07 08:34:44 PM PDT 24
Finished Jun 07 08:34:50 PM PDT 24
Peak memory 218516 kb
Host smart-cfc51241-3fa2-4d7e-a709-d1b3af54daae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725645835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.725645835
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.3691786734
Short name T408
Test name
Test status
Simulation time 16804275 ps
CPU time 0.9 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 206512 kb
Host smart-82cdeb95-5ce7-4e6c-ba15-6949ce6cc887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691786734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3691786734
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.751198035
Short name T45
Test name
Test status
Simulation time 20420694 ps
CPU time 0.87 seconds
Started Jun 07 08:33:13 PM PDT 24
Finished Jun 07 08:33:17 PM PDT 24
Peak memory 207040 kb
Host smart-e546347a-93e9-404e-9404-ebc5954a6cbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751198035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.751198035
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3399129930
Short name T199
Test name
Test status
Simulation time 22683955 ps
CPU time 1 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 219404 kb
Host smart-25909c50-f1f2-4e4c-bd19-4ba82afb9699
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399129930 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3399129930
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1816604223
Short name T472
Test name
Test status
Simulation time 25606941 ps
CPU time 0.91 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:24 PM PDT 24
Peak memory 218696 kb
Host smart-1fb1c2c1-e164-4cef-8e5f-d1586a0e0c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816604223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1816604223
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3936227800
Short name T429
Test name
Test status
Simulation time 119282875 ps
CPU time 1.27 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:26 PM PDT 24
Peak memory 218572 kb
Host smart-437ebec6-beb4-4bab-9d24-db7457948670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936227800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3936227800
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2842972163
Short name T71
Test name
Test status
Simulation time 28089095 ps
CPU time 0.87 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 215320 kb
Host smart-b978ce4f-e986-42f9-9ef4-b28b5266eec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842972163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2842972163
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.4216194609
Short name T321
Test name
Test status
Simulation time 24902248 ps
CPU time 0.93 seconds
Started Jun 07 08:33:15 PM PDT 24
Finished Jun 07 08:33:19 PM PDT 24
Peak memory 215192 kb
Host smart-b58ea828-922d-4d5e-a11f-7d16b88c9d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216194609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4216194609
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1420624865
Short name T221
Test name
Test status
Simulation time 600163278 ps
CPU time 5.97 seconds
Started Jun 07 08:33:15 PM PDT 24
Finished Jun 07 08:33:24 PM PDT 24
Peak memory 220316 kb
Host smart-32e3e010-556f-4793-8286-51b890cacd8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420624865 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1420624865
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1015764519
Short name T393
Test name
Test status
Simulation time 60053102056 ps
CPU time 176.9 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:36:28 PM PDT 24
Peak memory 218472 kb
Host smart-42420170-fa40-4312-bc6e-563d44c5d761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015764519 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1015764519
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2213579862
Short name T568
Test name
Test status
Simulation time 442763308 ps
CPU time 1.76 seconds
Started Jun 07 08:34:25 PM PDT 24
Finished Jun 07 08:34:37 PM PDT 24
Peak memory 218280 kb
Host smart-ff37e411-6521-428d-9150-a31ccc11704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213579862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2213579862
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1645392757
Short name T786
Test name
Test status
Simulation time 89346020 ps
CPU time 1.1 seconds
Started Jun 07 08:34:24 PM PDT 24
Finished Jun 07 08:34:36 PM PDT 24
Peak memory 217176 kb
Host smart-85214dec-c9fe-4ea6-93f3-40e575b99659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645392757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1645392757
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2267826383
Short name T13
Test name
Test status
Simulation time 61053125 ps
CPU time 1.35 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:34:33 PM PDT 24
Peak memory 219632 kb
Host smart-f50b36a9-9941-4261-90cb-0033a579e47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267826383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2267826383
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2740323023
Short name T729
Test name
Test status
Simulation time 28806472 ps
CPU time 1.04 seconds
Started Jun 07 08:34:17 PM PDT 24
Finished Jun 07 08:34:28 PM PDT 24
Peak memory 216764 kb
Host smart-4b4882d5-09ae-4e45-9938-6e0fc318d665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740323023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2740323023
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3462414790
Short name T386
Test name
Test status
Simulation time 226299107 ps
CPU time 3.35 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:32 PM PDT 24
Peak memory 219836 kb
Host smart-906f6a5a-9ccd-415f-8ddb-6aada1636e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462414790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3462414790
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2433714535
Short name T675
Test name
Test status
Simulation time 231114134 ps
CPU time 1.19 seconds
Started Jun 07 08:34:32 PM PDT 24
Finished Jun 07 08:34:42 PM PDT 24
Peak memory 218228 kb
Host smart-6d9d8602-2d3a-4be4-b44c-2505ce435ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433714535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2433714535
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3719470447
Short name T535
Test name
Test status
Simulation time 61510738 ps
CPU time 1.12 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:29 PM PDT 24
Peak memory 218368 kb
Host smart-47d79aa4-025a-4341-936d-c8c0efabab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719470447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3719470447
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3060688892
Short name T344
Test name
Test status
Simulation time 312751086 ps
CPU time 4 seconds
Started Jun 07 08:34:32 PM PDT 24
Finished Jun 07 08:34:45 PM PDT 24
Peak memory 219940 kb
Host smart-8f416cb5-3deb-4aae-b95d-b685f677cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060688892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3060688892
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1127237986
Short name T522
Test name
Test status
Simulation time 71954052 ps
CPU time 1.68 seconds
Started Jun 07 08:34:17 PM PDT 24
Finished Jun 07 08:34:27 PM PDT 24
Peak memory 218264 kb
Host smart-f3f33573-7612-432f-9bd7-7791af19efaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127237986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1127237986
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1320867772
Short name T341
Test name
Test status
Simulation time 78512676 ps
CPU time 1.11 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 218264 kb
Host smart-8cb3a79c-30cc-4164-83ed-d6fc56797007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320867772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1320867772
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3897876962
Short name T681
Test name
Test status
Simulation time 24933670 ps
CPU time 1.19 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:24 PM PDT 24
Peak memory 219268 kb
Host smart-1a0b3e22-25be-49eb-a430-9d224aece296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897876962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3897876962
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.25737583
Short name T449
Test name
Test status
Simulation time 27727977 ps
CPU time 0.93 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 206564 kb
Host smart-264d7b06-3215-4ee3-9726-61409d20d150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25737583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.25737583
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.307157613
Short name T828
Test name
Test status
Simulation time 70376817 ps
CPU time 1.2 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 216520 kb
Host smart-fb082ce6-9a1f-4796-8530-3be2ac0cc72d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307157613 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.307157613
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2352252216
Short name T174
Test name
Test status
Simulation time 19687560 ps
CPU time 1.13 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:25 PM PDT 24
Peak memory 224072 kb
Host smart-6bebf6ee-2b21-450e-a78f-7c55edb51417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352252216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2352252216
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3744098492
Short name T684
Test name
Test status
Simulation time 74794333 ps
CPU time 1.22 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 218336 kb
Host smart-86798d89-3ae4-4df4-9da2-61ab06a2ecc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744098492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3744098492
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3855768164
Short name T433
Test name
Test status
Simulation time 22725277 ps
CPU time 1.13 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 215552 kb
Host smart-9555be7d-2367-4347-a681-1d3233850a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855768164 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3855768164
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2945843829
Short name T623
Test name
Test status
Simulation time 15419539 ps
CPU time 0.96 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 215224 kb
Host smart-720d2d67-e53d-470c-bd0b-a544c6882eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945843829 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2945843829
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.4060156532
Short name T96
Test name
Test status
Simulation time 722408011 ps
CPU time 3.86 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 216944 kb
Host smart-098a1604-d751-44cf-81da-53ad5badb0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060156532 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4060156532
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2253599699
Short name T630
Test name
Test status
Simulation time 25365063940 ps
CPU time 289.02 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:38:15 PM PDT 24
Peak memory 223264 kb
Host smart-8cee810b-220a-4488-a8bb-494e92dbfd4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253599699 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2253599699
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3133691116
Short name T725
Test name
Test status
Simulation time 275025481 ps
CPU time 3.5 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:36 PM PDT 24
Peak memory 219928 kb
Host smart-49e40e97-db11-40d6-804d-c8497a9aecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133691116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3133691116
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3846454324
Short name T281
Test name
Test status
Simulation time 111768979 ps
CPU time 1.28 seconds
Started Jun 07 08:34:27 PM PDT 24
Finished Jun 07 08:34:38 PM PDT 24
Peak memory 218524 kb
Host smart-2790683b-d85f-4cf3-ad03-e7eb838634ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846454324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3846454324
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3158994525
Short name T489
Test name
Test status
Simulation time 144624097 ps
CPU time 1.79 seconds
Started Jun 07 08:34:24 PM PDT 24
Finished Jun 07 08:34:37 PM PDT 24
Peak memory 220044 kb
Host smart-228a1911-7741-4e59-bd47-a1c860e4882b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158994525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3158994525
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3047176529
Short name T294
Test name
Test status
Simulation time 322913268 ps
CPU time 3.42 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 219744 kb
Host smart-ff2a8ac0-318e-4bc3-b356-ebc0ff8be977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047176529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3047176529
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.4029185804
Short name T385
Test name
Test status
Simulation time 129007422 ps
CPU time 2.94 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:34:34 PM PDT 24
Peak memory 217020 kb
Host smart-9d3998b1-69d9-4db5-8cc6-54d90c158eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029185804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4029185804
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3366209723
Short name T450
Test name
Test status
Simulation time 56155943 ps
CPU time 1.62 seconds
Started Jun 07 08:34:15 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 218248 kb
Host smart-5fe1bd66-6d44-4d24-b5ea-b7cd8e59a687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366209723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3366209723
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1475947166
Short name T478
Test name
Test status
Simulation time 92097723 ps
CPU time 1.33 seconds
Started Jun 07 08:34:20 PM PDT 24
Finished Jun 07 08:34:32 PM PDT 24
Peak memory 216980 kb
Host smart-c0b91c88-0efc-45b5-9d0f-87626ab28b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475947166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1475947166
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.708539107
Short name T361
Test name
Test status
Simulation time 46092482 ps
CPU time 1.07 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:23 PM PDT 24
Peak memory 218472 kb
Host smart-107f9404-1134-4f02-9885-f7137be5b909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708539107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.708539107
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1400598146
Short name T440
Test name
Test status
Simulation time 46445852 ps
CPU time 1.02 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:33 PM PDT 24
Peak memory 217088 kb
Host smart-1667bf2b-71d1-4239-95a4-08718140144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400598146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1400598146
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.2635865131
Short name T785
Test name
Test status
Simulation time 18532727 ps
CPU time 0.82 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:31 PM PDT 24
Peak memory 206308 kb
Host smart-04626324-b219-4438-8c9e-19816f0dda35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635865131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2635865131
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1681477622
Short name T812
Test name
Test status
Simulation time 11239938 ps
CPU time 0.85 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 216232 kb
Host smart-25438a00-64aa-47b7-a156-75e59a5e9320
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681477622 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1681477622
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.1254295059
Short name T113
Test name
Test status
Simulation time 43985453 ps
CPU time 1.12 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 219756 kb
Host smart-9e77c18c-367c-4a6f-9999-bb07927c84a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254295059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1254295059
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2470319346
Short name T591
Test name
Test status
Simulation time 164047745 ps
CPU time 2.15 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:25 PM PDT 24
Peak memory 219568 kb
Host smart-065c5886-3fc6-4dab-8be3-c5a4a4b78bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470319346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2470319346
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1232451962
Short name T745
Test name
Test status
Simulation time 27801523 ps
CPU time 1.06 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 224004 kb
Host smart-fb235490-fd9d-4df7-be81-52c906978364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232451962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1232451962
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2452187341
Short name T316
Test name
Test status
Simulation time 41543267 ps
CPU time 0.95 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:31 PM PDT 24
Peak memory 207032 kb
Host smart-39ab1940-1cc8-4e1f-9a55-00d171c519f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452187341 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2452187341
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1093399950
Short name T627
Test name
Test status
Simulation time 550241014 ps
CPU time 3.25 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:35 PM PDT 24
Peak memory 216712 kb
Host smart-b0579231-851b-4fcb-83bc-adfb9bc8d0e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093399950 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1093399950
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2747994067
Short name T776
Test name
Test status
Simulation time 539601724135 ps
CPU time 1227.91 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:54:01 PM PDT 24
Peak memory 231196 kb
Host smart-b651561f-5eec-441c-a1ad-6a3fc9631b67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747994067 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2747994067
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4213727281
Short name T831
Test name
Test status
Simulation time 61692881 ps
CPU time 1.83 seconds
Started Jun 07 08:34:27 PM PDT 24
Finished Jun 07 08:34:40 PM PDT 24
Peak memory 217392 kb
Host smart-c4d3e82f-bffc-4ade-a1bb-7d173b75a50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213727281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4213727281
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2292023834
Short name T303
Test name
Test status
Simulation time 76017897 ps
CPU time 2.55 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:32 PM PDT 24
Peak memory 218468 kb
Host smart-d635e272-1b35-4c4a-8294-714a30aaae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292023834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2292023834
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3541178267
Short name T594
Test name
Test status
Simulation time 38978506 ps
CPU time 1.01 seconds
Started Jun 07 08:34:20 PM PDT 24
Finished Jun 07 08:34:31 PM PDT 24
Peak memory 216992 kb
Host smart-9df037b4-66d8-4a61-9c03-b37cd29c4355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541178267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3541178267
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1741223965
Short name T209
Test name
Test status
Simulation time 43096062 ps
CPU time 1.17 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:34:32 PM PDT 24
Peak memory 217960 kb
Host smart-c9de1f5c-a023-4763-af0f-573c65daebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741223965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1741223965
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.918646330
Short name T337
Test name
Test status
Simulation time 69275920 ps
CPU time 1.18 seconds
Started Jun 07 08:34:24 PM PDT 24
Finished Jun 07 08:34:44 PM PDT 24
Peak memory 216908 kb
Host smart-2d592ec0-32c4-40ab-9a8a-d1cbb4f82b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918646330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.918646330
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2674765674
Short name T291
Test name
Test status
Simulation time 49310905 ps
CPU time 1.48 seconds
Started Jun 07 08:34:33 PM PDT 24
Finished Jun 07 08:34:43 PM PDT 24
Peak memory 218192 kb
Host smart-28ad0b7c-3a9c-4101-adeb-3a6ca9ef5ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674765674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2674765674
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3677224040
Short name T538
Test name
Test status
Simulation time 86590566 ps
CPU time 1.93 seconds
Started Jun 07 08:34:35 PM PDT 24
Finished Jun 07 08:34:45 PM PDT 24
Peak memory 219468 kb
Host smart-152de56a-69fc-471b-9146-1bea2ebaed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677224040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3677224040
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3466348343
Short name T287
Test name
Test status
Simulation time 102173937 ps
CPU time 2.19 seconds
Started Jun 07 08:34:44 PM PDT 24
Finished Jun 07 08:34:50 PM PDT 24
Peak memory 219508 kb
Host smart-216a52aa-bda2-4627-b818-1de545edb0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466348343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3466348343
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.587065988
Short name T374
Test name
Test status
Simulation time 43903852 ps
CPU time 1.69 seconds
Started Jun 07 08:34:17 PM PDT 24
Finished Jun 07 08:34:33 PM PDT 24
Peak memory 218216 kb
Host smart-811166d1-70a6-4c11-961b-3b124971c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587065988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.587065988
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3950263053
Short name T260
Test name
Test status
Simulation time 54516369 ps
CPU time 1.23 seconds
Started Jun 07 08:34:25 PM PDT 24
Finished Jun 07 08:34:37 PM PDT 24
Peak memory 217004 kb
Host smart-bac92098-d06a-4c88-ab22-3396d584e4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950263053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3950263053
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.1760796315
Short name T417
Test name
Test status
Simulation time 26741884 ps
CPU time 0.84 seconds
Started Jun 07 08:33:28 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 206412 kb
Host smart-77ade08b-0d2d-4fb9-90a3-b20cc2ba8f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760796315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1760796315
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2768867380
Short name T645
Test name
Test status
Simulation time 53260036 ps
CPU time 0.86 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 216208 kb
Host smart-1712bd37-d658-4b6c-ab58-56487650ed42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768867380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2768867380
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.3408694942
Short name T129
Test name
Test status
Simulation time 30314438 ps
CPU time 1 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 219492 kb
Host smart-0b111261-496b-462d-a53e-36a018bcb9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408694942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3408694942
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.549515597
Short name T290
Test name
Test status
Simulation time 49011693 ps
CPU time 1.3 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:35 PM PDT 24
Peak memory 218148 kb
Host smart-95dcef83-d047-446f-9689-d7268b96f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549515597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.549515597
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1415789347
Short name T29
Test name
Test status
Simulation time 29827048 ps
CPU time 0.85 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 215636 kb
Host smart-17cf5e9f-bc7c-439d-b86e-d2cb9e238dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415789347 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1415789347
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1975659358
Short name T555
Test name
Test status
Simulation time 49296155 ps
CPU time 0.88 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 215232 kb
Host smart-2981d86c-de93-4f22-b43f-b9feec1c65e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975659358 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1975659358
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2504037491
Short name T829
Test name
Test status
Simulation time 406109663 ps
CPU time 4.66 seconds
Started Jun 07 08:33:27 PM PDT 24
Finished Jun 07 08:33:41 PM PDT 24
Peak memory 217160 kb
Host smart-cd4d9410-8f63-409e-aa54-bd4d49217de9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504037491 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2504037491
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/282.edn_genbits.165935860
Short name T309
Test name
Test status
Simulation time 85798477 ps
CPU time 1.2 seconds
Started Jun 07 08:34:23 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 219124 kb
Host smart-7dfe37e2-c409-4381-a324-c5ecf80126cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165935860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.165935860
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1644300171
Short name T416
Test name
Test status
Simulation time 173720972 ps
CPU time 1.27 seconds
Started Jun 07 08:34:23 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 218196 kb
Host smart-cb837ca7-3506-4848-9fd3-23411ef75369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644300171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1644300171
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2920238173
Short name T396
Test name
Test status
Simulation time 99942448 ps
CPU time 1.24 seconds
Started Jun 07 08:34:28 PM PDT 24
Finished Jun 07 08:34:39 PM PDT 24
Peak memory 216868 kb
Host smart-aff224be-b834-43cf-9272-63209c0a178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920238173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2920238173
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3729733110
Short name T619
Test name
Test status
Simulation time 34703869 ps
CPU time 1.36 seconds
Started Jun 07 08:34:53 PM PDT 24
Finished Jun 07 08:34:59 PM PDT 24
Peak memory 219080 kb
Host smart-4eb1e87e-b0a8-489b-b8cb-1d1a524c278a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729733110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3729733110
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.4282408051
Short name T228
Test name
Test status
Simulation time 152837075 ps
CPU time 1.48 seconds
Started Jun 07 08:34:33 PM PDT 24
Finished Jun 07 08:34:43 PM PDT 24
Peak memory 217128 kb
Host smart-c380c09f-06e5-4c9f-8593-c49aa3aafbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282408051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4282408051
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3423816666
Short name T651
Test name
Test status
Simulation time 36261929 ps
CPU time 1.34 seconds
Started Jun 07 08:34:46 PM PDT 24
Finished Jun 07 08:34:51 PM PDT 24
Peak memory 219576 kb
Host smart-1bc76095-ca78-43e2-80f4-741adc70b714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423816666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3423816666
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1241111892
Short name T592
Test name
Test status
Simulation time 35314906 ps
CPU time 1.2 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:35:13 PM PDT 24
Peak memory 218808 kb
Host smart-e6139668-ca80-4919-9fca-a444fa101aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241111892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1241111892
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3881776130
Short name T788
Test name
Test status
Simulation time 30770356 ps
CPU time 1.3 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 218044 kb
Host smart-011a61a5-d74f-4d0a-932d-dd59363e0e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881776130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3881776130
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2946939829
Short name T635
Test name
Test status
Simulation time 49959700 ps
CPU time 0.93 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 206576 kb
Host smart-caf89cce-1424-4ddf-9466-c2253309bd80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946939829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2946939829
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2898934915
Short name T93
Test name
Test status
Simulation time 182417379 ps
CPU time 1.01 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 217024 kb
Host smart-48118e63-a7b4-48d9-b6fb-c90e6a5a6b15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898934915 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2898934915
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.460314307
Short name T179
Test name
Test status
Simulation time 34954082 ps
CPU time 0.82 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 218164 kb
Host smart-7dc33460-45d7-448b-b112-d0e83922f292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460314307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.460314307
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2083743759
Short name T530
Test name
Test status
Simulation time 224478698 ps
CPU time 1.48 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 218428 kb
Host smart-9c6727b4-9316-4c06-9bb0-aab8e4a61aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083743759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2083743759
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4237119325
Short name T4
Test name
Test status
Simulation time 26687959 ps
CPU time 0.98 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 215780 kb
Host smart-38291832-8479-4a23-a37e-d5cd051b737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237119325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4237119325
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2226622580
Short name T789
Test name
Test status
Simulation time 16435380 ps
CPU time 0.92 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 215248 kb
Host smart-23d1f2e9-7395-49cb-9717-fee43c6f2d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226622580 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2226622580
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.39305836
Short name T832
Test name
Test status
Simulation time 360433025 ps
CPU time 3.78 seconds
Started Jun 07 08:33:18 PM PDT 24
Finished Jun 07 08:33:26 PM PDT 24
Peak memory 218020 kb
Host smart-e2303251-5ed5-4a55-bfc4-e6d72d0547d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39305836 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.39305836
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.4293637191
Short name T227
Test name
Test status
Simulation time 14347661969 ps
CPU time 318.76 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:38:54 PM PDT 24
Peak memory 217372 kb
Host smart-e39233c7-a4be-409f-b553-0e5667ba1878
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293637191 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.4293637191
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1644253717
Short name T359
Test name
Test status
Simulation time 67167783 ps
CPU time 1.1 seconds
Started Jun 07 08:34:26 PM PDT 24
Finished Jun 07 08:34:38 PM PDT 24
Peak memory 216952 kb
Host smart-827bc764-819c-4885-b704-b26598760db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644253717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1644253717
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3004082562
Short name T409
Test name
Test status
Simulation time 89645664 ps
CPU time 1.22 seconds
Started Jun 07 08:34:58 PM PDT 24
Finished Jun 07 08:35:05 PM PDT 24
Peak memory 217008 kb
Host smart-8972f641-acdb-4598-bb08-02c60e667535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004082562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3004082562
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1954628818
Short name T553
Test name
Test status
Simulation time 31213230 ps
CPU time 1.27 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:34:56 PM PDT 24
Peak memory 218156 kb
Host smart-a5ba4b6e-9935-410b-8e1b-69f5726135e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954628818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1954628818
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3740455542
Short name T798
Test name
Test status
Simulation time 42170237 ps
CPU time 1.17 seconds
Started Jun 07 08:34:35 PM PDT 24
Finished Jun 07 08:34:44 PM PDT 24
Peak memory 216964 kb
Host smart-93b52929-c228-46c9-9d04-b62375f60788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740455542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3740455542
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.349587973
Short name T749
Test name
Test status
Simulation time 42943891 ps
CPU time 1.57 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 215188 kb
Host smart-6e423b80-34b9-4497-a06b-1ff254d8de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349587973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.349587973
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1781881550
Short name T494
Test name
Test status
Simulation time 33189491 ps
CPU time 1.4 seconds
Started Jun 07 08:34:46 PM PDT 24
Finished Jun 07 08:34:51 PM PDT 24
Peak memory 218272 kb
Host smart-4fbfa9c8-0fe5-420a-9c18-0c280548c34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781881550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1781881550
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.961717199
Short name T722
Test name
Test status
Simulation time 41529559 ps
CPU time 1.5 seconds
Started Jun 07 08:34:24 PM PDT 24
Finished Jun 07 08:34:36 PM PDT 24
Peak memory 218376 kb
Host smart-12c15feb-435c-4991-9ab3-a387d8a25930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961717199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.961717199
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.4054136384
Short name T484
Test name
Test status
Simulation time 56360641 ps
CPU time 1.01 seconds
Started Jun 07 08:34:35 PM PDT 24
Finished Jun 07 08:34:44 PM PDT 24
Peak memory 217040 kb
Host smart-19aeb99f-8245-49be-87e6-b4bc1ad81373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054136384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4054136384
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2474781734
Short name T769
Test name
Test status
Simulation time 48333646 ps
CPU time 1.9 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:34 PM PDT 24
Peak memory 218196 kb
Host smart-26caab5b-e3f1-4db8-a45a-f26718c66dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474781734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2474781734
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.252476063
Short name T27
Test name
Test status
Simulation time 27779999 ps
CPU time 1.23 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 219288 kb
Host smart-094a2c26-bd5d-4134-8aed-c365e0b15db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252476063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.252476063
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1714649680
Short name T656
Test name
Test status
Simulation time 58027509 ps
CPU time 0.95 seconds
Started Jun 07 08:32:59 PM PDT 24
Finished Jun 07 08:33:04 PM PDT 24
Peak memory 214760 kb
Host smart-0cb3efd3-f913-4f8b-ab2d-3f0d3da0e6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714649680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1714649680
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1371622837
Short name T567
Test name
Test status
Simulation time 39958511 ps
CPU time 0.91 seconds
Started Jun 07 08:32:46 PM PDT 24
Finished Jun 07 08:32:54 PM PDT 24
Peak memory 216140 kb
Host smart-01f34170-9335-465a-a698-339331a273d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371622837 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1371622837
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3976843619
Short name T329
Test name
Test status
Simulation time 81514011 ps
CPU time 1.02 seconds
Started Jun 07 08:32:46 PM PDT 24
Finished Jun 07 08:32:54 PM PDT 24
Peak memory 219344 kb
Host smart-8dbf19f7-058b-45e9-a29d-cadfd0f60c23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976843619 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3976843619
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3591020575
Short name T643
Test name
Test status
Simulation time 19740702 ps
CPU time 1.22 seconds
Started Jun 07 08:32:57 PM PDT 24
Finished Jun 07 08:33:02 PM PDT 24
Peak memory 224136 kb
Host smart-ecf83bf6-2111-4324-8505-1ebce190f67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591020575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3591020575
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2533226075
Short name T428
Test name
Test status
Simulation time 147205266 ps
CPU time 1.27 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 218348 kb
Host smart-90d163f6-ae05-495e-92bf-10936e7766c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533226075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2533226075
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3681206467
Short name T362
Test name
Test status
Simulation time 37246373 ps
CPU time 0.87 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 215328 kb
Host smart-eb88488c-6da3-42dd-9c87-4173531bd8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681206467 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3681206467
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3726440144
Short name T272
Test name
Test status
Simulation time 16896351 ps
CPU time 0.98 seconds
Started Jun 07 08:32:44 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 207092 kb
Host smart-6b998a73-330f-476f-aedf-cbc758c49f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726440144 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3726440144
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2200312972
Short name T64
Test name
Test status
Simulation time 661784902 ps
CPU time 10.08 seconds
Started Jun 07 08:32:39 PM PDT 24
Finished Jun 07 08:32:59 PM PDT 24
Peak memory 235284 kb
Host smart-ad2d6cd1-6190-4ccd-95f0-695924b58f3a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200312972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2200312972
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3606603519
Short name T848
Test name
Test status
Simulation time 60878427 ps
CPU time 0.9 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 215204 kb
Host smart-6aa43324-4054-4d93-b88f-c7acc6e49b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606603519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3606603519
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3958795537
Short name T505
Test name
Test status
Simulation time 336940813 ps
CPU time 6.49 seconds
Started Jun 07 08:32:36 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 216932 kb
Host smart-52fbd363-c323-4390-bae2-c0a386bb52ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958795537 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3958795537
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1567311807
Short name T537
Test name
Test status
Simulation time 80375348346 ps
CPU time 551.98 seconds
Started Jun 07 08:32:33 PM PDT 24
Finished Jun 07 08:41:56 PM PDT 24
Peak memory 220368 kb
Host smart-092a8439-954b-4fcb-9141-5d8b3f7729bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567311807 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1567311807
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3877910877
Short name T116
Test name
Test status
Simulation time 40419063 ps
CPU time 1.24 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 218392 kb
Host smart-eecdfe0c-2fa8-4547-acaa-bcb2cf6f427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877910877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3877910877
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4077874955
Short name T526
Test name
Test status
Simulation time 45171555 ps
CPU time 0.92 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 214716 kb
Host smart-96c81180-258b-48e0-9f9c-97e842ff8f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077874955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4077874955
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.851938425
Short name T615
Test name
Test status
Simulation time 11848691 ps
CPU time 0.85 seconds
Started Jun 07 08:33:27 PM PDT 24
Finished Jun 07 08:33:37 PM PDT 24
Peak memory 216148 kb
Host smart-bcf6a2d7-5f91-49bb-8514-2d645a616bc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851938425 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.851938425
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1865862192
Short name T804
Test name
Test status
Simulation time 23232030 ps
CPU time 1.07 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 215688 kb
Host smart-9ebb5a69-d07b-4823-a6b1-031717dacd22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865862192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1865862192
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2145209689
Short name T427
Test name
Test status
Simulation time 63444883 ps
CPU time 1.05 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 220676 kb
Host smart-10335668-125d-4fa4-948f-2521f9f13b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145209689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2145209689
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2771382715
Short name T301
Test name
Test status
Simulation time 114845658 ps
CPU time 1.61 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 218248 kb
Host smart-adcf9a4e-f79a-46cd-be69-38fecdcb47e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771382715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2771382715
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.569291087
Short name T795
Test name
Test status
Simulation time 36897740 ps
CPU time 0.85 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 215752 kb
Host smart-42cf2389-5294-44c2-b534-68fab8bf8054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569291087 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.569291087
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1509157996
Short name T823
Test name
Test status
Simulation time 29882933 ps
CPU time 0.94 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:33:35 PM PDT 24
Peak memory 215160 kb
Host smart-60fdd2d5-281a-4f51-b2d6-24d6de06b349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509157996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1509157996
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3111208446
Short name T556
Test name
Test status
Simulation time 771491208 ps
CPU time 3.7 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:33 PM PDT 24
Peak memory 215208 kb
Host smart-72a0ed0f-9c07-4a56-a1bd-a9939ad41476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111208446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3111208446
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3415389960
Short name T370
Test name
Test status
Simulation time 129389178185 ps
CPU time 1492.49 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:58:22 PM PDT 24
Peak memory 224296 kb
Host smart-d546eb99-d728-4d4b-93ea-12bbc4b875d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415389960 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3415389960
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.296839567
Short name T177
Test name
Test status
Simulation time 28095711 ps
CPU time 1.28 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 218504 kb
Host smart-225ae96b-273e-4b69-a25e-ac254fdf2b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296839567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.296839567
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1639751231
Short name T447
Test name
Test status
Simulation time 48079639 ps
CPU time 0.87 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:26 PM PDT 24
Peak memory 214716 kb
Host smart-0d075504-749f-4484-83c1-1e12143519f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639751231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1639751231
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2995763844
Short name T42
Test name
Test status
Simulation time 33766408 ps
CPU time 0.8 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:31 PM PDT 24
Peak memory 216308 kb
Host smart-bf789e23-6014-4304-ae98-c495e580f441
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995763844 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2995763844
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.1059548799
Short name T503
Test name
Test status
Simulation time 20262761 ps
CPU time 1.16 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 224036 kb
Host smart-74043891-4662-44aa-b56c-a29f42da756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059548799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1059548799
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1008355787
Short name T405
Test name
Test status
Simulation time 37057536 ps
CPU time 1.4 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 218012 kb
Host smart-ea50c572-1939-4525-936b-d8b1db690570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008355787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1008355787
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3830571131
Short name T90
Test name
Test status
Simulation time 37723773 ps
CPU time 0.87 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:57 PM PDT 24
Peak memory 215820 kb
Host smart-894a8649-0b85-4561-b911-ae5a907ba53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830571131 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3830571131
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2020013024
Short name T625
Test name
Test status
Simulation time 18337288 ps
CPU time 0.99 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:31 PM PDT 24
Peak memory 215220 kb
Host smart-297adc3b-d712-4435-bd8a-bce368507cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020013024 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2020013024
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3563412551
Short name T688
Test name
Test status
Simulation time 78940974 ps
CPU time 1.95 seconds
Started Jun 07 08:33:29 PM PDT 24
Finished Jun 07 08:33:40 PM PDT 24
Peak memory 216696 kb
Host smart-cd0147e7-ad5f-45ec-8acf-cb571a029b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563412551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3563412551
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.310412064
Short name T715
Test name
Test status
Simulation time 84309667522 ps
CPU time 978.81 seconds
Started Jun 07 08:33:43 PM PDT 24
Finished Jun 07 08:50:04 PM PDT 24
Peak memory 222060 kb
Host smart-84c8589c-0dd5-4f15-990f-9c4310693d1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310412064 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.310412064
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2808062401
Short name T108
Test name
Test status
Simulation time 71713390 ps
CPU time 1.08 seconds
Started Jun 07 08:33:32 PM PDT 24
Finished Jun 07 08:33:41 PM PDT 24
Peak memory 218248 kb
Host smart-70b6a454-b308-4555-b1f9-02e23b0142d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808062401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2808062401
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.937662019
Short name T327
Test name
Test status
Simulation time 19633377 ps
CPU time 1 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:33 PM PDT 24
Peak memory 206644 kb
Host smart-8dcc9386-a747-49e9-aa02-ea67f48841af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937662019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.937662019
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2093951517
Short name T70
Test name
Test status
Simulation time 18305454 ps
CPU time 0.83 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:33 PM PDT 24
Peak memory 216148 kb
Host smart-6ad3fa09-a604-427d-8e5a-db6798682cb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093951517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2093951517
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.2676125436
Short name T153
Test name
Test status
Simulation time 29465491 ps
CPU time 0.83 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 218304 kb
Host smart-c75c6704-89ca-44fc-b47d-f08e5e41d6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676125436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2676125436
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1097471869
Short name T320
Test name
Test status
Simulation time 36255040 ps
CPU time 1.23 seconds
Started Jun 07 08:33:28 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 219568 kb
Host smart-2e5c7042-4320-4508-a7b0-1b6bc59aba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097471869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1097471869
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_smoke.3158775699
Short name T639
Test name
Test status
Simulation time 18371586 ps
CPU time 0.97 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 215240 kb
Host smart-485bac2d-e9da-402a-a1ad-b1006bd9d755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158775699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3158775699
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2010342414
Short name T224
Test name
Test status
Simulation time 49192123 ps
CPU time 1.55 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:35 PM PDT 24
Peak memory 216788 kb
Host smart-3d657c4b-f2b2-414f-9e5d-016aa682db9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010342414 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2010342414
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1306222939
Short name T791
Test name
Test status
Simulation time 54037667695 ps
CPU time 596.32 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:43:25 PM PDT 24
Peak memory 218608 kb
Host smart-352cccf9-60f3-4845-ad84-4190c380d86b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306222939 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1306222939
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2250904456
Short name T167
Test name
Test status
Simulation time 74049564 ps
CPU time 1.09 seconds
Started Jun 07 08:33:32 PM PDT 24
Finished Jun 07 08:33:43 PM PDT 24
Peak memory 219692 kb
Host smart-807111c6-68a4-48a6-8cfa-438c0801201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250904456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2250904456
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.35408920
Short name T611
Test name
Test status
Simulation time 36056913 ps
CPU time 0.8 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 214540 kb
Host smart-9214d28e-ff4f-4ab1-8ec6-816175a812ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35408920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.35408920
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2327104993
Short name T821
Test name
Test status
Simulation time 23850918 ps
CPU time 0.82 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:33 PM PDT 24
Peak memory 215300 kb
Host smart-4f0e61d6-2195-43d8-b24d-ba2a8710471e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327104993 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2327104993
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.20331508
Short name T120
Test name
Test status
Simulation time 43671919 ps
CPU time 1.36 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:28 PM PDT 24
Peak memory 216772 kb
Host smart-29e15c47-2be1-4610-bcd1-e217cc8f3a0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20331508 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_dis
able_auto_req_mode.20331508
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2208843632
Short name T162
Test name
Test status
Simulation time 23520924 ps
CPU time 0.97 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 218056 kb
Host smart-36fd8604-3a46-4d33-b8fa-feb663e1a685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208843632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2208843632
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4039030849
Short name T808
Test name
Test status
Simulation time 88932120 ps
CPU time 1.34 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 218212 kb
Host smart-4a4ed06e-3b60-4875-9626-d7436cbd7c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039030849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4039030849
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3757390278
Short name T811
Test name
Test status
Simulation time 24697574 ps
CPU time 0.88 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:27 PM PDT 24
Peak memory 215912 kb
Host smart-3b688388-cb53-44bc-b77c-2092c00181d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757390278 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3757390278
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2417030480
Short name T465
Test name
Test status
Simulation time 32446958 ps
CPU time 0.94 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:33 PM PDT 24
Peak memory 215220 kb
Host smart-a78c79af-6a18-4096-a7f5-d635dc26701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417030480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2417030480
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3565679213
Short name T380
Test name
Test status
Simulation time 287774930 ps
CPU time 5.21 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 216900 kb
Host smart-96d5d764-51fd-428b-afda-a2abec693c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565679213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3565679213
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1036406805
Short name T807
Test name
Test status
Simulation time 8366549599 ps
CPU time 94.53 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:35:10 PM PDT 24
Peak memory 217840 kb
Host smart-339bf989-4c03-4f39-94c6-c4d6d5146c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036406805 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1036406805
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.400820889
Short name T152
Test name
Test status
Simulation time 45454309 ps
CPU time 1.18 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 220800 kb
Host smart-c77edd41-d419-4262-a4c6-4d49b91a65b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400820889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.400820889
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1809210350
Short name T373
Test name
Test status
Simulation time 34053506 ps
CPU time 0.86 seconds
Started Jun 07 08:33:44 PM PDT 24
Finished Jun 07 08:33:47 PM PDT 24
Peak memory 214728 kb
Host smart-94ec2d1e-9cc3-4355-a395-bf397b029180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809210350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1809210350
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1797087672
Short name T383
Test name
Test status
Simulation time 40406410 ps
CPU time 1.29 seconds
Started Jun 07 08:33:20 PM PDT 24
Finished Jun 07 08:33:29 PM PDT 24
Peak memory 216720 kb
Host smart-129add59-0e39-4f6f-bfd1-91c2f66aef51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797087672 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1797087672
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.117806149
Short name T142
Test name
Test status
Simulation time 23413916 ps
CPU time 1.16 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 220252 kb
Host smart-042f38d7-0a38-4898-a659-25e9324fd5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117806149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.117806149
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.888111185
Short name T557
Test name
Test status
Simulation time 65193543 ps
CPU time 1.33 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 216860 kb
Host smart-4fbf197f-ee2b-4445-8a48-a89a2e15a296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888111185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.888111185
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1143665361
Short name T826
Test name
Test status
Simulation time 37136132 ps
CPU time 1 seconds
Started Jun 07 08:33:42 PM PDT 24
Finished Jun 07 08:33:46 PM PDT 24
Peak memory 223856 kb
Host smart-c971f12a-7082-40af-b092-48af2589db0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143665361 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1143665361
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1586187415
Short name T654
Test name
Test status
Simulation time 25539086 ps
CPU time 0.91 seconds
Started Jun 07 08:33:26 PM PDT 24
Finished Jun 07 08:33:37 PM PDT 24
Peak memory 215224 kb
Host smart-5fccbac5-2ddf-4c54-b3d6-c15f45a96a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586187415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1586187415
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3426297549
Short name T757
Test name
Test status
Simulation time 166999267 ps
CPU time 1.46 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 216792 kb
Host smart-a9809979-5dae-401f-abde-49e3ccf48a2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426297549 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3426297549
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3937399918
Short name T759
Test name
Test status
Simulation time 77429040384 ps
CPU time 1883.98 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 09:04:56 PM PDT 24
Peak memory 228088 kb
Host smart-500b98b6-41f3-4da3-bc07-d3a3ccdd1547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937399918 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3937399918
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1397715874
Short name T278
Test name
Test status
Simulation time 22893700 ps
CPU time 1.11 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 218184 kb
Host smart-f2570848-14cd-4bcb-9d39-11118aacedfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397715874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1397715874
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1690115869
Short name T800
Test name
Test status
Simulation time 16248346 ps
CPU time 0.83 seconds
Started Jun 07 08:33:26 PM PDT 24
Finished Jun 07 08:33:37 PM PDT 24
Peak memory 206036 kb
Host smart-e6824c7f-b487-4229-92cf-6a2c53cb0e16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690115869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1690115869
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3107954264
Short name T774
Test name
Test status
Simulation time 12086505 ps
CPU time 0.83 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 215848 kb
Host smart-baebfd6e-2410-4fb1-ab43-3f97e9f6ec62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107954264 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3107954264
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2882138016
Short name T700
Test name
Test status
Simulation time 139375921 ps
CPU time 1.11 seconds
Started Jun 07 08:33:46 PM PDT 24
Finished Jun 07 08:33:49 PM PDT 24
Peak memory 216680 kb
Host smart-af6762b9-5ff7-43b8-acd9-2519d218176b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882138016 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2882138016
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1655977890
Short name T182
Test name
Test status
Simulation time 44700583 ps
CPU time 0.88 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:25 PM PDT 24
Peak memory 219044 kb
Host smart-187555aa-d74e-4fea-b368-8fe6dc7d32f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655977890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1655977890
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3200714780
Short name T618
Test name
Test status
Simulation time 64552396 ps
CPU time 1.1 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:32 PM PDT 24
Peak memory 216952 kb
Host smart-9876769b-d883-42ca-a034-caf038acd524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200714780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3200714780
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4123454804
Short name T34
Test name
Test status
Simulation time 22732214 ps
CPU time 0.94 seconds
Started Jun 07 08:33:19 PM PDT 24
Finished Jun 07 08:33:26 PM PDT 24
Peak memory 215868 kb
Host smart-b128dedc-4d4c-44a5-b007-10820b9a348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123454804 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4123454804
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1203145296
Short name T608
Test name
Test status
Simulation time 28093334 ps
CPU time 0.96 seconds
Started Jun 07 08:33:48 PM PDT 24
Finished Jun 07 08:33:51 PM PDT 24
Peak memory 215144 kb
Host smart-e658ba5b-e6cc-4404-bddf-215949d8cdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203145296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1203145296
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.15085545
Short name T54
Test name
Test status
Simulation time 246910569 ps
CPU time 1.77 seconds
Started Jun 07 08:33:27 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 219496 kb
Host smart-5d3b7652-eabb-4564-8827-e3f7535f7cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15085545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.15085545
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1341337252
Short name T214
Test name
Test status
Simulation time 50243006894 ps
CPU time 536.08 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:42:24 PM PDT 24
Peak memory 218400 kb
Host smart-f02db103-65bf-40ae-920e-e9f4506e3fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341337252 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1341337252
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2365714785
Short name T157
Test name
Test status
Simulation time 32214783 ps
CPU time 1.27 seconds
Started Jun 07 08:33:28 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 219300 kb
Host smart-d639cd4e-0cb7-4c7f-91fb-f88a3280f981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365714785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2365714785
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3318805612
Short name T668
Test name
Test status
Simulation time 22535700 ps
CPU time 0.86 seconds
Started Jun 07 08:33:31 PM PDT 24
Finished Jun 07 08:33:40 PM PDT 24
Peak memory 206304 kb
Host smart-a8d4c2e0-be8f-4eb8-814f-58bf13b5db0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318805612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3318805612
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1127475988
Short name T825
Test name
Test status
Simulation time 10693370 ps
CPU time 0.9 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 215836 kb
Host smart-a26973e6-8aa6-4ee9-be25-6b685e0a989c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127475988 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1127475988
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.3456944626
Short name T838
Test name
Test status
Simulation time 53350503 ps
CPU time 1.26 seconds
Started Jun 07 08:34:01 PM PDT 24
Finished Jun 07 08:34:08 PM PDT 24
Peak memory 219668 kb
Host smart-d7006f9a-9c85-44d6-9bc8-4c46efecafcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456944626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3456944626
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.650084548
Short name T10
Test name
Test status
Simulation time 112093035 ps
CPU time 1.43 seconds
Started Jun 07 08:33:26 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 219852 kb
Host smart-033d62f9-a8c8-41b9-b72d-a07700132726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650084548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.650084548
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2380540991
Short name T766
Test name
Test status
Simulation time 23052445 ps
CPU time 1.04 seconds
Started Jun 07 08:33:31 PM PDT 24
Finished Jun 07 08:33:40 PM PDT 24
Peak memory 215600 kb
Host smart-38b9484f-f33a-4156-a07a-7135b0d6f20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380540991 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2380540991
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3307987762
Short name T609
Test name
Test status
Simulation time 16997589 ps
CPU time 1 seconds
Started Jun 07 08:33:26 PM PDT 24
Finished Jun 07 08:33:37 PM PDT 24
Peak memory 215200 kb
Host smart-fb4853df-e6de-4ec9-bc5b-5fb4e2b566b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307987762 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3307987762
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1334877976
Short name T68
Test name
Test status
Simulation time 295151458 ps
CPU time 5.86 seconds
Started Jun 07 08:33:28 PM PDT 24
Finished Jun 07 08:33:43 PM PDT 24
Peak memory 216808 kb
Host smart-a10546bf-8af6-4dec-97eb-0cadc71b3f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334877976 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1334877976
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.464801946
Short name T215
Test name
Test status
Simulation time 25687345068 ps
CPU time 544.92 seconds
Started Jun 07 08:33:39 PM PDT 24
Finished Jun 07 08:42:48 PM PDT 24
Peak memory 223352 kb
Host smart-a3b6dc19-12e2-472d-84c2-5ca05e7b6c12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464801946 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.464801946
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2683791305
Short name T166
Test name
Test status
Simulation time 31363596 ps
CPU time 1.26 seconds
Started Jun 07 08:33:41 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 215648 kb
Host smart-83c9a4c8-425c-4beb-9a16-2f5375359ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683791305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2683791305
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.789772273
Short name T577
Test name
Test status
Simulation time 16890687 ps
CPU time 0.95 seconds
Started Jun 07 08:33:47 PM PDT 24
Finished Jun 07 08:33:51 PM PDT 24
Peak memory 206632 kb
Host smart-077cf540-46e8-4e4f-90e0-bcbc0eab7884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789772273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.789772273
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1983169209
Short name T593
Test name
Test status
Simulation time 18614271 ps
CPU time 0.85 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:31 PM PDT 24
Peak memory 215968 kb
Host smart-ecba6c7f-6cb0-493f-be98-1ab7cfe34dcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983169209 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1983169209
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3013951035
Short name T545
Test name
Test status
Simulation time 53513190 ps
CPU time 0.99 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:57 PM PDT 24
Peak memory 216688 kb
Host smart-5b4411da-22fa-498a-bcd0-2f330d109c95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013951035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3013951035
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3277559856
Short name T155
Test name
Test status
Simulation time 20136256 ps
CPU time 1.03 seconds
Started Jun 07 08:33:41 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 224016 kb
Host smart-922dca70-9707-4f9d-96ed-e98d1db9bf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277559856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3277559856
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.953328684
Short name T302
Test name
Test status
Simulation time 58548826 ps
CPU time 1.25 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 218204 kb
Host smart-cbbaa72d-bc7a-412a-9836-ef62df0c8ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953328684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.953328684
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2059225594
Short name T663
Test name
Test status
Simulation time 21869591 ps
CPU time 1.11 seconds
Started Jun 07 08:33:59 PM PDT 24
Finished Jun 07 08:34:06 PM PDT 24
Peak memory 215372 kb
Host smart-8d903e8a-f5e5-4f1c-983c-f5d31211a588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059225594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2059225594
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.831083218
Short name T463
Test name
Test status
Simulation time 42485647 ps
CPU time 0.95 seconds
Started Jun 07 08:33:43 PM PDT 24
Finished Jun 07 08:33:46 PM PDT 24
Peak memory 215292 kb
Host smart-93fb5ce0-799a-4798-acaa-28ad496919bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831083218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.831083218
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3032617151
Short name T222
Test name
Test status
Simulation time 323451204 ps
CPU time 1.17 seconds
Started Jun 07 08:33:31 PM PDT 24
Finished Jun 07 08:33:40 PM PDT 24
Peak memory 206476 kb
Host smart-c8271db7-6871-49b8-9214-0ef15463c900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032617151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3032617151
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3343493779
Short name T213
Test name
Test status
Simulation time 113533106529 ps
CPU time 584.33 seconds
Started Jun 07 08:33:27 PM PDT 24
Finished Jun 07 08:43:21 PM PDT 24
Peak memory 221536 kb
Host smart-c653b3a2-e28d-4587-8517-c79f33cafb96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343493779 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3343493779
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.813882295
Short name T104
Test name
Test status
Simulation time 43547479 ps
CPU time 1.14 seconds
Started Jun 07 08:33:49 PM PDT 24
Finished Jun 07 08:33:52 PM PDT 24
Peak memory 219180 kb
Host smart-2349c7d8-d284-4e75-90ff-6936668691c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813882295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.813882295
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2355146652
Short name T375
Test name
Test status
Simulation time 23002387 ps
CPU time 1.02 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 214740 kb
Host smart-3c025773-519c-4b8c-ad37-f7e56e81df7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355146652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2355146652
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2295866205
Short name T188
Test name
Test status
Simulation time 37231321 ps
CPU time 0.88 seconds
Started Jun 07 08:33:27 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 216128 kb
Host smart-83ee55e1-9af7-4623-8890-f274a20cf07f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295866205 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2295866205
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.783103738
Short name T573
Test name
Test status
Simulation time 34743743 ps
CPU time 1.21 seconds
Started Jun 07 08:33:31 PM PDT 24
Finished Jun 07 08:33:40 PM PDT 24
Peak memory 216716 kb
Host smart-2730d494-6029-43c9-bf28-8b00ef712a7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783103738 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.783103738
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1826573315
Short name T22
Test name
Test status
Simulation time 25189393 ps
CPU time 0.86 seconds
Started Jun 07 08:33:40 PM PDT 24
Finished Jun 07 08:33:44 PM PDT 24
Peak memory 218116 kb
Host smart-7981883a-7d08-4a98-bbbc-edde35f32a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826573315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1826573315
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.16985936
Short name T340
Test name
Test status
Simulation time 37902155 ps
CPU time 1.57 seconds
Started Jun 07 08:33:27 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 218208 kb
Host smart-977540c3-c71a-4f47-8891-c4a1c8c2f464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16985936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.16985936
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1496312953
Short name T86
Test name
Test status
Simulation time 21776815 ps
CPU time 1.02 seconds
Started Jun 07 08:33:46 PM PDT 24
Finished Jun 07 08:33:49 PM PDT 24
Peak memory 215816 kb
Host smart-453de133-4da0-4e12-811f-a84509732747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496312953 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1496312953
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1610799467
Short name T378
Test name
Test status
Simulation time 38402776 ps
CPU time 0.87 seconds
Started Jun 07 08:33:27 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 215180 kb
Host smart-5c2df536-3234-46f3-894f-66fb10cf6e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610799467 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1610799467
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1349974437
Short name T607
Test name
Test status
Simulation time 22083105 ps
CPU time 1.06 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 215244 kb
Host smart-66d7c4e0-ab2b-45bd-a3bf-8111edf86163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349974437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1349974437
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1241528091
Short name T430
Test name
Test status
Simulation time 20957124691 ps
CPU time 561.49 seconds
Started Jun 07 08:33:26 PM PDT 24
Finished Jun 07 08:42:58 PM PDT 24
Peak memory 223572 kb
Host smart-7cf613cc-28f6-4f31-9226-02e7bd0a9384
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241528091 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1241528091
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.931642318
Short name T105
Test name
Test status
Simulation time 68087155 ps
CPU time 1.26 seconds
Started Jun 07 08:33:25 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 219440 kb
Host smart-61ed647c-dcd8-484d-9964-14688f99a928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931642318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.931642318
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.4150878986
Short name T392
Test name
Test status
Simulation time 49614750 ps
CPU time 0.85 seconds
Started Jun 07 08:33:33 PM PDT 24
Finished Jun 07 08:33:41 PM PDT 24
Peak memory 206536 kb
Host smart-e74754d9-798e-46bd-9755-8f25b85609fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150878986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.4150878986
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2473921983
Short name T145
Test name
Test status
Simulation time 87941983 ps
CPU time 1.13 seconds
Started Jun 07 08:33:56 PM PDT 24
Finished Jun 07 08:34:02 PM PDT 24
Peak memory 216568 kb
Host smart-3ba74dab-a9bd-4601-a75e-7ce5182c816e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473921983 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2473921983
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.393987329
Short name T418
Test name
Test status
Simulation time 43211581 ps
CPU time 0.92 seconds
Started Jun 07 08:33:22 PM PDT 24
Finished Jun 07 08:33:31 PM PDT 24
Peak memory 232132 kb
Host smart-54ece221-6679-4ebe-8d99-9a9618791cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393987329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.393987329
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2543058676
Short name T20
Test name
Test status
Simulation time 189042216 ps
CPU time 2.94 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 217184 kb
Host smart-9809f523-2a4f-4db3-97dd-b1d5d5c4c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543058676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2543058676
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4125035594
Short name T467
Test name
Test status
Simulation time 21479636 ps
CPU time 1.06 seconds
Started Jun 07 08:33:49 PM PDT 24
Finished Jun 07 08:33:52 PM PDT 24
Peak memory 215512 kb
Host smart-bde053bc-724a-496b-8f24-84dc0eb85935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125035594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4125035594
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3913256858
Short name T443
Test name
Test status
Simulation time 28503886 ps
CPU time 0.96 seconds
Started Jun 07 08:34:07 PM PDT 24
Finished Jun 07 08:34:13 PM PDT 24
Peak memory 215216 kb
Host smart-6d599af8-2983-4571-b8b6-a2b391978154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913256858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3913256858
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3233970517
Short name T223
Test name
Test status
Simulation time 269857344 ps
CPU time 2.98 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:34:01 PM PDT 24
Peak memory 216932 kb
Host smart-25a66f72-755f-4dfb-90fe-d86cd03f7a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233970517 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3233970517
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.461941879
Short name T737
Test name
Test status
Simulation time 302806206217 ps
CPU time 1981.08 seconds
Started Jun 07 08:33:28 PM PDT 24
Finished Jun 07 09:06:38 PM PDT 24
Peak memory 228636 kb
Host smart-5072629f-f113-4f95-ba13-c73941075ae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461941879 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.461941879
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1517079977
Short name T719
Test name
Test status
Simulation time 42323554 ps
CPU time 1.19 seconds
Started Jun 07 08:33:10 PM PDT 24
Finished Jun 07 08:33:14 PM PDT 24
Peak memory 218212 kb
Host smart-b2790a77-e5bc-4b82-9b59-bc3d2cdcb6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517079977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1517079977
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.469350500
Short name T569
Test name
Test status
Simulation time 40151647 ps
CPU time 0.92 seconds
Started Jun 07 08:32:43 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 206496 kb
Host smart-170a85da-7838-4afb-82c2-a82900b9ed90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469350500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.469350500
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3529295051
Short name T190
Test name
Test status
Simulation time 11936376 ps
CPU time 0.89 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 216328 kb
Host smart-3189ed69-82ad-4240-8554-c7ac7b15e2f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529295051 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3529295051
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3796692149
Short name T138
Test name
Test status
Simulation time 220935603 ps
CPU time 1.39 seconds
Started Jun 07 08:32:47 PM PDT 24
Finished Jun 07 08:32:55 PM PDT 24
Peak memory 216920 kb
Host smart-e6dd9933-69bf-49c4-b416-0ef095c23124
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796692149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3796692149
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3134740309
Short name T740
Test name
Test status
Simulation time 23757168 ps
CPU time 1.04 seconds
Started Jun 07 08:32:39 PM PDT 24
Finished Jun 07 08:32:51 PM PDT 24
Peak memory 229612 kb
Host smart-83e49188-0427-4c33-b001-214b2119e884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134740309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3134740309
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_intr.3216487714
Short name T624
Test name
Test status
Simulation time 21134287 ps
CPU time 1.1 seconds
Started Jun 07 08:32:48 PM PDT 24
Finished Jun 07 08:32:55 PM PDT 24
Peak memory 215788 kb
Host smart-7eb0c7aa-672e-4143-bbe3-5bd4f9cfb13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216487714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3216487714
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1979778148
Short name T23
Test name
Test status
Simulation time 17979782 ps
CPU time 0.98 seconds
Started Jun 07 08:32:39 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 206992 kb
Host smart-8e76271f-4bf7-4a6f-aeba-8497cd47dc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979778148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1979778148
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2203966590
Short name T65
Test name
Test status
Simulation time 460535418 ps
CPU time 6.79 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 237196 kb
Host smart-b721c750-0fa9-4d69-9783-ab59af3ff519
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203966590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2203966590
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3379952433
Short name T696
Test name
Test status
Simulation time 31481058 ps
CPU time 0.95 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 215220 kb
Host smart-7ef1c7fb-4b3d-4e3d-8f7a-611af68578ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379952433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3379952433
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3401311794
Short name T708
Test name
Test status
Simulation time 643871360 ps
CPU time 4.03 seconds
Started Jun 07 08:32:51 PM PDT 24
Finished Jun 07 08:33:00 PM PDT 24
Peak memory 215172 kb
Host smart-05bc76aa-e223-4f4f-b3bf-2606a995492a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401311794 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3401311794
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2541729975
Short name T399
Test name
Test status
Simulation time 29587114174 ps
CPU time 259.09 seconds
Started Jun 07 08:33:01 PM PDT 24
Finished Jun 07 08:37:24 PM PDT 24
Peak memory 216448 kb
Host smart-e00445ae-1df2-4655-b4c5-9a5571419e57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541729975 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2541729975
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1082500256
Short name T103
Test name
Test status
Simulation time 66635553 ps
CPU time 1.07 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:05 PM PDT 24
Peak memory 218260 kb
Host smart-5bed07e5-0136-4551-84bb-0e581cd48b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082500256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1082500256
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3093987971
Short name T500
Test name
Test status
Simulation time 93563245 ps
CPU time 0.76 seconds
Started Jun 07 08:33:45 PM PDT 24
Finished Jun 07 08:33:48 PM PDT 24
Peak memory 206180 kb
Host smart-6c9c22cd-a1d5-41bc-a18c-50578f242f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093987971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3093987971
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.897774397
Short name T820
Test name
Test status
Simulation time 99744072 ps
CPU time 0.86 seconds
Started Jun 07 08:33:27 PM PDT 24
Finished Jun 07 08:33:40 PM PDT 24
Peak memory 216224 kb
Host smart-08e21e9b-a13b-41d2-85e0-c0433c6cf663
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897774397 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.897774397
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3749898687
Short name T470
Test name
Test status
Simulation time 71557550 ps
CPU time 1.03 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 215504 kb
Host smart-dfc4dd6e-952f-4601-aefa-c3f780936afe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749898687 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3749898687
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1254555723
Short name T8
Test name
Test status
Simulation time 25595685 ps
CPU time 1.19 seconds
Started Jun 07 08:33:26 PM PDT 24
Finished Jun 07 08:33:37 PM PDT 24
Peak memory 218536 kb
Host smart-e7eb3826-e7b0-45f4-89e1-0d28354a612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254555723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1254555723
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1692640180
Short name T586
Test name
Test status
Simulation time 102473720 ps
CPU time 1.15 seconds
Started Jun 07 08:33:41 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 219424 kb
Host smart-7a8ff270-e13e-47c9-a519-791b3ca92397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692640180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1692640180
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2866773988
Short name T89
Test name
Test status
Simulation time 22023086 ps
CPU time 1.05 seconds
Started Jun 07 08:33:28 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 215776 kb
Host smart-70bde148-b4be-47c5-a6ce-fb0d17b2bdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866773988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2866773988
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3359999094
Short name T705
Test name
Test status
Simulation time 33221470 ps
CPU time 0.9 seconds
Started Jun 07 08:33:21 PM PDT 24
Finished Jun 07 08:33:30 PM PDT 24
Peak memory 215160 kb
Host smart-6d624667-6dee-42a9-84b6-4fce1e788e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359999094 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3359999094
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1891809364
Short name T730
Test name
Test status
Simulation time 948605942 ps
CPU time 4.2 seconds
Started Jun 07 08:33:29 PM PDT 24
Finished Jun 07 08:33:42 PM PDT 24
Peak memory 216964 kb
Host smart-14589789-f864-401f-8e34-394e01195c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891809364 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1891809364
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_alert.955011659
Short name T117
Test name
Test status
Simulation time 127592716 ps
CPU time 1.22 seconds
Started Jun 07 08:33:27 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 218836 kb
Host smart-d3d0c25d-1a2f-4742-aeb5-4e89a3ec62c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955011659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.955011659
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3884229800
Short name T501
Test name
Test status
Simulation time 34319845 ps
CPU time 0.87 seconds
Started Jun 07 08:33:30 PM PDT 24
Finished Jun 07 08:33:40 PM PDT 24
Peak memory 205836 kb
Host smart-c47ed768-a6a0-4e57-bc1f-e0c4c44de71a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884229800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3884229800
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.825415354
Short name T844
Test name
Test status
Simulation time 115157555 ps
CPU time 0.9 seconds
Started Jun 07 08:34:02 PM PDT 24
Finished Jun 07 08:34:09 PM PDT 24
Peak memory 215268 kb
Host smart-2f8473c4-31c9-45b8-9f6e-cd77f04749a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825415354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.825415354
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2674357701
Short name T119
Test name
Test status
Simulation time 33500313 ps
CPU time 1.16 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 216796 kb
Host smart-0e357718-2d72-465f-90ec-7611350ca466
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674357701 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2674357701
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3636906841
Short name T168
Test name
Test status
Simulation time 29489859 ps
CPU time 0.85 seconds
Started Jun 07 08:34:07 PM PDT 24
Finished Jun 07 08:34:13 PM PDT 24
Peak memory 217952 kb
Host smart-c8b69ba3-7c07-46bf-9b1c-6b2e05e1f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636906841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3636906841
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.248072163
Short name T384
Test name
Test status
Simulation time 49073354 ps
CPU time 1.58 seconds
Started Jun 07 08:33:26 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 218260 kb
Host smart-30e55176-17eb-47ed-b3e0-35194ddff64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248072163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.248072163
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.442768748
Short name T610
Test name
Test status
Simulation time 24793576 ps
CPU time 0.94 seconds
Started Jun 07 08:33:52 PM PDT 24
Finished Jun 07 08:33:55 PM PDT 24
Peak memory 215292 kb
Host smart-95419ab8-11b2-4694-95e7-77ae3618672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442768748 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.442768748
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3854307473
Short name T571
Test name
Test status
Simulation time 81333595 ps
CPU time 0.86 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:57 PM PDT 24
Peak memory 215148 kb
Host smart-5870b7dc-060e-4a03-961f-0021f1ce96bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854307473 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3854307473
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.853870681
Short name T540
Test name
Test status
Simulation time 614161494 ps
CPU time 3.43 seconds
Started Jun 07 08:33:26 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 217024 kb
Host smart-5e967c0a-15ba-4c48-89b4-18d3eaa6b626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853870681 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.853870681
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert_test.1413673638
Short name T562
Test name
Test status
Simulation time 25894863 ps
CPU time 0.86 seconds
Started Jun 07 08:33:23 PM PDT 24
Finished Jun 07 08:33:33 PM PDT 24
Peak memory 206512 kb
Host smart-eaffeb0b-d731-44f8-81de-115151fc288c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413673638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1413673638
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2671587382
Short name T82
Test name
Test status
Simulation time 45629622 ps
CPU time 1.13 seconds
Started Jun 07 08:34:03 PM PDT 24
Finished Jun 07 08:34:10 PM PDT 24
Peak memory 218348 kb
Host smart-0acfe713-f27e-465e-80a9-529e15d16fe7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671587382 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2671587382
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3610910189
Short name T432
Test name
Test status
Simulation time 84393524 ps
CPU time 1.12 seconds
Started Jun 07 08:33:28 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 219564 kb
Host smart-7db67334-22e5-467d-a77b-415ff7c72835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610910189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3610910189
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3561925845
Short name T842
Test name
Test status
Simulation time 54429132 ps
CPU time 1.23 seconds
Started Jun 07 08:34:02 PM PDT 24
Finished Jun 07 08:34:09 PM PDT 24
Peak memory 218076 kb
Host smart-e58eec29-dfd2-48f1-9aaf-569a6dbed370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561925845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3561925845
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2094830822
Short name T33
Test name
Test status
Simulation time 28095592 ps
CPU time 0.84 seconds
Started Jun 07 08:34:03 PM PDT 24
Finished Jun 07 08:34:09 PM PDT 24
Peak memory 215528 kb
Host smart-b020111b-ae5e-4a46-b9d0-600f3c65ec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094830822 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2094830822
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3832075440
Short name T422
Test name
Test status
Simulation time 211858545 ps
CPU time 0.97 seconds
Started Jun 07 08:33:59 PM PDT 24
Finished Jun 07 08:34:05 PM PDT 24
Peak memory 215180 kb
Host smart-77cced9e-f009-4db5-ad13-8ff58da9f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832075440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3832075440
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3836034680
Short name T343
Test name
Test status
Simulation time 281990082 ps
CPU time 6.17 seconds
Started Jun 07 08:33:52 PM PDT 24
Finished Jun 07 08:34:02 PM PDT 24
Peak memory 216932 kb
Host smart-dd5af0a4-28c5-41cb-b7bf-aca5a631117d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836034680 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3836034680
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3612155572
Short name T403
Test name
Test status
Simulation time 11630008186 ps
CPU time 302.46 seconds
Started Jun 07 08:33:29 PM PDT 24
Finished Jun 07 08:38:41 PM PDT 24
Peak memory 218048 kb
Host smart-bea677f4-158d-48d9-ac6b-63e2ae49b726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612155572 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3612155572
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert_test.144945126
Short name T226
Test name
Test status
Simulation time 19410959 ps
CPU time 0.82 seconds
Started Jun 07 08:33:24 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 206668 kb
Host smart-a97e58bf-3680-4426-94af-c0071a79bfbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144945126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.144945126
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2175338596
Short name T464
Test name
Test status
Simulation time 21707504 ps
CPU time 0.91 seconds
Started Jun 07 08:33:56 PM PDT 24
Finished Jun 07 08:34:02 PM PDT 24
Peak memory 215312 kb
Host smart-8b28e8cc-8291-44dd-b2e5-0eaafbd5d53e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175338596 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2175338596
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3896265343
Short name T257
Test name
Test status
Simulation time 86650533 ps
CPU time 1.1 seconds
Started Jun 07 08:33:36 PM PDT 24
Finished Jun 07 08:33:42 PM PDT 24
Peak memory 216692 kb
Host smart-ad0291f2-0f12-4b97-895c-9047b3cb9f20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896265343 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3896265343
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.104756593
Short name T674
Test name
Test status
Simulation time 19476710 ps
CPU time 1.02 seconds
Started Jun 07 08:34:03 PM PDT 24
Finished Jun 07 08:34:10 PM PDT 24
Peak memory 218684 kb
Host smart-3e84b5ee-5298-4ede-8399-49d9b0b5f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104756593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.104756593
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_intr.4060602092
Short name T31
Test name
Test status
Simulation time 20686092 ps
CPU time 1.09 seconds
Started Jun 07 08:34:08 PM PDT 24
Finished Jun 07 08:34:15 PM PDT 24
Peak memory 215944 kb
Host smart-5fcb80a3-a674-47c7-a764-4a8990ae8060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060602092 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4060602092
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.787335391
Short name T391
Test name
Test status
Simulation time 39383699 ps
CPU time 0.91 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:57 PM PDT 24
Peak memory 207000 kb
Host smart-6abfca6b-89c2-4f40-a861-b33425ee0f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787335391 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.787335391
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3998636636
Short name T714
Test name
Test status
Simulation time 365401767 ps
CPU time 4 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:57 PM PDT 24
Peak memory 216920 kb
Host smart-6fd690c1-9cb9-4379-808e-70231a0ffd14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998636636 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3998636636
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.478060880
Short name T92
Test name
Test status
Simulation time 59475505956 ps
CPU time 673.87 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:45:10 PM PDT 24
Peak memory 218104 kb
Host smart-3ae86e6d-8cf6-4500-ab7c-37fc8aa883bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478060880 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.478060880
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.891846500
Short name T275
Test name
Test status
Simulation time 39783156 ps
CPU time 1.19 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 219148 kb
Host smart-aa90d5b9-3d8f-413c-b98f-71f4c3340431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891846500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.891846500
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3893086433
Short name T67
Test name
Test status
Simulation time 20406837 ps
CPU time 0.82 seconds
Started Jun 07 08:33:55 PM PDT 24
Finished Jun 07 08:34:01 PM PDT 24
Peak memory 206764 kb
Host smart-dbddfe29-ba6d-4c71-a76f-5b5b1fdd2c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893086433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3893086433
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3644094047
Short name T163
Test name
Test status
Simulation time 136398556 ps
CPU time 0.8 seconds
Started Jun 07 08:33:43 PM PDT 24
Finished Jun 07 08:33:46 PM PDT 24
Peak memory 216176 kb
Host smart-ca9ad48d-3e15-44a7-8c3b-84374cbabe93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644094047 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3644094047
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3813003252
Short name T140
Test name
Test status
Simulation time 78339322 ps
CPU time 1.35 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 219340 kb
Host smart-23e2e04f-25cd-4ff2-ac4d-4b4b05f1d7ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813003252 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3813003252
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.994604858
Short name T435
Test name
Test status
Simulation time 46540873 ps
CPU time 0.99 seconds
Started Jun 07 08:34:02 PM PDT 24
Finished Jun 07 08:34:09 PM PDT 24
Peak memory 218408 kb
Host smart-7bfa7b1b-f985-4980-a8f1-c845a3fb016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994604858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.994604858
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1908061918
Short name T533
Test name
Test status
Simulation time 49558790 ps
CPU time 1.13 seconds
Started Jun 07 08:33:35 PM PDT 24
Finished Jun 07 08:33:42 PM PDT 24
Peak memory 216920 kb
Host smart-f33f43a0-de68-4ce0-b487-bc39eb53ad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908061918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1908061918
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1541197334
Short name T461
Test name
Test status
Simulation time 39336084 ps
CPU time 0.99 seconds
Started Jun 07 08:33:28 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 224136 kb
Host smart-cbcdaa20-834d-480e-b037-b88de32f518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541197334 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1541197334
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.565984911
Short name T547
Test name
Test status
Simulation time 42168753 ps
CPU time 0.88 seconds
Started Jun 07 08:33:47 PM PDT 24
Finished Jun 07 08:33:50 PM PDT 24
Peak memory 215216 kb
Host smart-3d8b9896-1469-402a-baf5-9101150a1ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565984911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.565984911
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2430495244
Short name T56
Test name
Test status
Simulation time 1803733085 ps
CPU time 4.93 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:34:02 PM PDT 24
Peak memory 216804 kb
Host smart-0db4156d-f5c9-4e0e-8f1f-b50576e1f1e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430495244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2430495244
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2147868342
Short name T833
Test name
Test status
Simulation time 37480794718 ps
CPU time 325.9 seconds
Started Jun 07 08:33:31 PM PDT 24
Finished Jun 07 08:39:05 PM PDT 24
Peak memory 217664 kb
Host smart-f6041545-cb1e-44fa-9be7-4816af2d5b77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147868342 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2147868342
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.505222683
Short name T351
Test name
Test status
Simulation time 68994390 ps
CPU time 1.32 seconds
Started Jun 07 08:34:01 PM PDT 24
Finished Jun 07 08:34:09 PM PDT 24
Peak memory 206840 kb
Host smart-c7f02538-4918-4b13-aa16-ec6ee806b229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505222683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.505222683
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.97493330
Short name T742
Test name
Test status
Simulation time 20446594 ps
CPU time 0.89 seconds
Started Jun 07 08:33:55 PM PDT 24
Finished Jun 07 08:34:01 PM PDT 24
Peak memory 216132 kb
Host smart-24b00b5c-36a4-4646-8de8-fc3719c2e077
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97493330 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.97493330
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1464960038
Short name T365
Test name
Test status
Simulation time 127389586 ps
CPU time 0.99 seconds
Started Jun 07 08:34:00 PM PDT 24
Finished Jun 07 08:34:06 PM PDT 24
Peak memory 216680 kb
Host smart-cb4b3da7-e5b3-4a3e-9702-c1ef02c882d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464960038 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1464960038
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2632043900
Short name T146
Test name
Test status
Simulation time 19675068 ps
CPU time 1.23 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 224084 kb
Host smart-3923142c-58fd-49ea-8aab-ca8f7573460f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632043900 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2632043900
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3537853665
Short name T741
Test name
Test status
Simulation time 43241248 ps
CPU time 1.19 seconds
Started Jun 07 08:33:36 PM PDT 24
Finished Jun 07 08:33:43 PM PDT 24
Peak memory 218240 kb
Host smart-3761caa1-07af-40c3-b3e8-e72efc29af5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537853665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3537853665
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3771026745
Short name T100
Test name
Test status
Simulation time 22547535 ps
CPU time 1.09 seconds
Started Jun 07 08:33:49 PM PDT 24
Finished Jun 07 08:33:52 PM PDT 24
Peak memory 215512 kb
Host smart-7382e019-a7b7-4ca3-8bf2-1baa80e0eabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771026745 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3771026745
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3771587038
Short name T570
Test name
Test status
Simulation time 42441732 ps
CPU time 0.89 seconds
Started Jun 07 08:33:55 PM PDT 24
Finished Jun 07 08:34:00 PM PDT 24
Peak memory 215212 kb
Host smart-e2560b25-47cc-4fe3-bc16-309f8e6d4299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771587038 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3771587038
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.821573983
Short name T596
Test name
Test status
Simulation time 366378288 ps
CPU time 3.9 seconds
Started Jun 07 08:33:47 PM PDT 24
Finished Jun 07 08:33:53 PM PDT 24
Peak memory 216724 kb
Host smart-95f49633-7616-41f2-8cca-109c1da2e04f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821573983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.821573983
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1377552530
Short name T751
Test name
Test status
Simulation time 632662226544 ps
CPU time 1630.04 seconds
Started Jun 07 08:34:02 PM PDT 24
Finished Jun 07 09:01:18 PM PDT 24
Peak memory 221856 kb
Host smart-b1320511-95db-48e5-81a0-28e90cb890b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377552530 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1377552530
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.4132803489
Short name T746
Test name
Test status
Simulation time 72366225 ps
CPU time 1.18 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 219052 kb
Host smart-a67177d2-7bd5-4246-b5ff-e7d0593f781c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132803489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.4132803489
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.74813423
Short name T716
Test name
Test status
Simulation time 21858653 ps
CPU time 1.05 seconds
Started Jun 07 08:34:03 PM PDT 24
Finished Jun 07 08:34:10 PM PDT 24
Peak memory 206652 kb
Host smart-a24fe1bb-21d9-4b3d-9989-25445a7dfc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74813423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.74813423
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1092795918
Short name T546
Test name
Test status
Simulation time 17915797 ps
CPU time 0.83 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 216092 kb
Host smart-4d68a1ec-3d53-442e-8084-b3dee41e9197
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092795918 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1092795918
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3010015631
Short name T504
Test name
Test status
Simulation time 36938471 ps
CPU time 1.22 seconds
Started Jun 07 08:33:39 PM PDT 24
Finished Jun 07 08:33:44 PM PDT 24
Peak memory 216856 kb
Host smart-69f000fc-7e43-490e-8e9f-057890276511
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010015631 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3010015631
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1560730384
Short name T225
Test name
Test status
Simulation time 38613919 ps
CPU time 0.99 seconds
Started Jun 07 08:33:41 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 218292 kb
Host smart-b8c3c500-00e5-49b1-83e8-6dfa11fcab8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560730384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1560730384
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3994781066
Short name T296
Test name
Test status
Simulation time 36332228 ps
CPU time 1.51 seconds
Started Jun 07 08:34:02 PM PDT 24
Finished Jun 07 08:34:10 PM PDT 24
Peak memory 217108 kb
Host smart-0c0abf31-1152-41ce-ba5e-91c44a63da60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994781066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3994781066
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2884847493
Short name T419
Test name
Test status
Simulation time 31540933 ps
CPU time 0.91 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 215536 kb
Host smart-caedc83a-e354-478a-9381-dcfc5fbc6254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884847493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2884847493
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.834779133
Short name T849
Test name
Test status
Simulation time 18470286 ps
CPU time 1.06 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:34:00 PM PDT 24
Peak memory 214684 kb
Host smart-b508c238-c72c-4739-bb80-33ce64e76e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834779133 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.834779133
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.765633559
Short name T565
Test name
Test status
Simulation time 449621618 ps
CPU time 5.14 seconds
Started Jun 07 08:33:56 PM PDT 24
Finished Jun 07 08:34:06 PM PDT 24
Peak memory 215204 kb
Host smart-fea72e2a-3d1f-49a9-ac07-738ded7a05b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765633559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.765633559
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1213767530
Short name T37
Test name
Test status
Simulation time 308615608741 ps
CPU time 1356.6 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:56:51 PM PDT 24
Peak memory 224108 kb
Host smart-79831b5f-3bb0-417e-86b8-36770688b46d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213767530 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1213767530
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2870587484
Short name T176
Test name
Test status
Simulation time 103588186 ps
CPU time 1.13 seconds
Started Jun 07 08:34:01 PM PDT 24
Finished Jun 07 08:34:08 PM PDT 24
Peak memory 219424 kb
Host smart-003ce46d-5085-4ee8-a11f-033ea9f20fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870587484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2870587484
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2620708347
Short name T387
Test name
Test status
Simulation time 86912385 ps
CPU time 1.05 seconds
Started Jun 07 08:34:01 PM PDT 24
Finished Jun 07 08:34:08 PM PDT 24
Peak memory 214776 kb
Host smart-7bf569b3-0995-48d1-80a0-b76991e46679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620708347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2620708347
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1245712212
Short name T149
Test name
Test status
Simulation time 12709334 ps
CPU time 0.87 seconds
Started Jun 07 08:33:59 PM PDT 24
Finished Jun 07 08:34:05 PM PDT 24
Peak memory 215308 kb
Host smart-67433104-af0b-4204-83bd-fde6f8ea7216
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245712212 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1245712212
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1893869883
Short name T143
Test name
Test status
Simulation time 35246048 ps
CPU time 1.24 seconds
Started Jun 07 08:33:59 PM PDT 24
Finished Jun 07 08:34:06 PM PDT 24
Peak memory 216784 kb
Host smart-80d9c139-6cf0-40a4-963f-3aba5aa5d460
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893869883 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1893869883
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2249708057
Short name T59
Test name
Test status
Simulation time 29119592 ps
CPU time 1.37 seconds
Started Jun 07 08:33:46 PM PDT 24
Finished Jun 07 08:33:50 PM PDT 24
Peak memory 225692 kb
Host smart-8ad8796b-33d1-4ff1-943d-1d62d43fb9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249708057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2249708057
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1700965329
Short name T47
Test name
Test status
Simulation time 77167123 ps
CPU time 1.72 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:58 PM PDT 24
Peak memory 218512 kb
Host smart-b932a761-f50f-4284-b339-54501f6688ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700965329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1700965329
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.305129198
Short name T752
Test name
Test status
Simulation time 25304990 ps
CPU time 0.98 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 215740 kb
Host smart-308112b9-0457-4754-8ad6-7e20aebb8f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305129198 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.305129198
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1563254274
Short name T331
Test name
Test status
Simulation time 18344729 ps
CPU time 1.07 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 215180 kb
Host smart-88a054f3-8e84-4a68-a6d6-703e845bd9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563254274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1563254274
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3083494666
Short name T835
Test name
Test status
Simulation time 921015687 ps
CPU time 3.62 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 216960 kb
Host smart-28e05c77-3827-4502-a102-aef016cafeb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083494666 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3083494666
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4021058166
Short name T496
Test name
Test status
Simulation time 41873549390 ps
CPU time 503.79 seconds
Started Jun 07 08:33:56 PM PDT 24
Finished Jun 07 08:42:26 PM PDT 24
Peak memory 216480 kb
Host smart-9c830f07-c695-4993-9aff-6b514390ef18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021058166 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4021058166
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.183481982
Short name T128
Test name
Test status
Simulation time 53559665 ps
CPU time 1.19 seconds
Started Jun 07 08:33:41 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 218220 kb
Host smart-12435260-69e5-4f3a-91e5-1b68311f4a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183481982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.183481982
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.107699220
Short name T631
Test name
Test status
Simulation time 22412844 ps
CPU time 1.08 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 206668 kb
Host smart-13c214de-0440-4189-b6d5-320a534eb2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107699220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.107699220
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1448421040
Short name T76
Test name
Test status
Simulation time 11695684 ps
CPU time 0.88 seconds
Started Jun 07 08:33:41 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 216500 kb
Host smart-c1644ec6-d569-426c-85a5-85f11bf94c10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448421040 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1448421040
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.878745430
Short name T678
Test name
Test status
Simulation time 218770035 ps
CPU time 1.1 seconds
Started Jun 07 08:34:01 PM PDT 24
Finished Jun 07 08:34:08 PM PDT 24
Peak memory 216740 kb
Host smart-3e65ba4a-92a8-47e3-a9d5-f97d4ab27f3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878745430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.878745430
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.4242138060
Short name T756
Test name
Test status
Simulation time 33329866 ps
CPU time 0.96 seconds
Started Jun 07 08:33:29 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 223856 kb
Host smart-30f754bc-2216-460b-ac58-916ebc066227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242138060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.4242138060
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.683248649
Short name T477
Test name
Test status
Simulation time 39319951 ps
CPU time 1.53 seconds
Started Jun 07 08:34:00 PM PDT 24
Finished Jun 07 08:34:07 PM PDT 24
Peak memory 218284 kb
Host smart-98bd229b-f733-4691-a0b6-27d8464ef08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683248649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.683248649
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.4013473776
Short name T524
Test name
Test status
Simulation time 23331988 ps
CPU time 1.09 seconds
Started Jun 07 08:33:52 PM PDT 24
Finished Jun 07 08:33:55 PM PDT 24
Peak memory 224072 kb
Host smart-9080f792-7662-4284-b29f-1514915a955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013473776 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.4013473776
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.4283440588
Short name T683
Test name
Test status
Simulation time 21190083 ps
CPU time 0.97 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 215212 kb
Host smart-bac86715-5962-4689-8b58-bcb12a967b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283440588 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.4283440588
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3384685662
Short name T534
Test name
Test status
Simulation time 383479644 ps
CPU time 4.23 seconds
Started Jun 07 08:33:35 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 216848 kb
Host smart-ae6c9523-6c1a-4b5a-a485-4035a054da18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384685662 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3384685662
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1817771057
Short name T680
Test name
Test status
Simulation time 28973755941 ps
CPU time 768.76 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:46:45 PM PDT 24
Peak memory 223652 kb
Host smart-ba61019b-a047-4f6f-afa1-25af6c6ab15c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817771057 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1817771057
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert_test.3242871939
Short name T614
Test name
Test status
Simulation time 21958831 ps
CPU time 0.82 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 206336 kb
Host smart-93db2b2e-eb24-4d81-9f34-692b8894a834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242871939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3242871939
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.486552367
Short name T814
Test name
Test status
Simulation time 82860880 ps
CPU time 0.83 seconds
Started Jun 07 08:33:41 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 216120 kb
Host smart-dc7a55e9-b2c4-40ec-bb28-4fb9cb38baa3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486552367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.486552367
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.424475427
Short name T415
Test name
Test status
Simulation time 22427972 ps
CPU time 1.09 seconds
Started Jun 07 08:34:06 PM PDT 24
Finished Jun 07 08:34:13 PM PDT 24
Peak memory 218272 kb
Host smart-3430609f-54ac-4590-bc93-42ce721fa3d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424475427 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.424475427
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2786784390
Short name T747
Test name
Test status
Simulation time 53691185 ps
CPU time 1 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 220728 kb
Host smart-cfc2bb67-1a71-4340-9dd8-03533e41e3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786784390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2786784390
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.852436742
Short name T658
Test name
Test status
Simulation time 109426676 ps
CPU time 1.07 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 216900 kb
Host smart-068d296d-119b-4530-a33b-ce71045e7485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852436742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.852436742
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.4012024084
Short name T258
Test name
Test status
Simulation time 21414939 ps
CPU time 1.07 seconds
Started Jun 07 08:33:46 PM PDT 24
Finished Jun 07 08:33:50 PM PDT 24
Peak memory 215440 kb
Host smart-ae1029a8-4541-4a5d-8ef9-a28dbcec9b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012024084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.4012024084
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3907978851
Short name T313
Test name
Test status
Simulation time 29755114 ps
CPU time 0.96 seconds
Started Jun 07 08:33:41 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 215224 kb
Host smart-c8d72956-2475-4b6e-b228-e4f66e6a5855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907978851 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3907978851
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.4271729662
Short name T621
Test name
Test status
Simulation time 611637357 ps
CPU time 3.35 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 216940 kb
Host smart-cef570f6-ec25-497a-a48f-95a5575a26db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271729662 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.4271729662
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1997747665
Short name T204
Test name
Test status
Simulation time 260204993679 ps
CPU time 1499.05 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:58:58 PM PDT 24
Peak memory 223316 kb
Host smart-ec06d0a0-6ab8-4cd4-a84a-c80a24ac87f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997747665 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1997747665
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert_test.2362179689
Short name T364
Test name
Test status
Simulation time 18127196 ps
CPU time 1.01 seconds
Started Jun 07 08:32:41 PM PDT 24
Finished Jun 07 08:32:52 PM PDT 24
Peak memory 206540 kb
Host smart-2e1143e1-6f88-4dfc-9b01-d80064ef8e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362179689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2362179689
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3391043118
Short name T801
Test name
Test status
Simulation time 100282300 ps
CPU time 0.86 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 215932 kb
Host smart-5e53892c-2de6-4b36-9c7e-e6eb49deabec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391043118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3391043118
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2262822932
Short name T132
Test name
Test status
Simulation time 37251513 ps
CPU time 1.02 seconds
Started Jun 07 08:32:46 PM PDT 24
Finished Jun 07 08:32:54 PM PDT 24
Peak memory 218224 kb
Host smart-3eeb1957-3633-4b0d-a99d-cff2aa0c07f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262822932 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2262822932
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1957528525
Short name T597
Test name
Test status
Simulation time 33844654 ps
CPU time 1 seconds
Started Jun 07 08:32:36 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 229408 kb
Host smart-67a32eef-68e1-4e51-bae3-702e9b1e4865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957528525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1957528525
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2756559087
Short name T483
Test name
Test status
Simulation time 74793327 ps
CPU time 1.5 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:48 PM PDT 24
Peak memory 219544 kb
Host smart-c4ae4f7b-a29b-4ea5-b697-426dd788d7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756559087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2756559087
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3270207450
Short name T771
Test name
Test status
Simulation time 38298654 ps
CPU time 0.84 seconds
Started Jun 07 08:32:36 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 215596 kb
Host smart-efa708c0-4bf8-4e81-aac6-3619da094786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270207450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3270207450
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3775965447
Short name T762
Test name
Test status
Simulation time 18017662 ps
CPU time 1.02 seconds
Started Jun 07 08:32:58 PM PDT 24
Finished Jun 07 08:33:03 PM PDT 24
Peak memory 207016 kb
Host smart-f1968e66-88d6-45c0-847c-b05047b129a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775965447 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3775965447
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3185203615
Short name T612
Test name
Test status
Simulation time 35898382 ps
CPU time 0.94 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 215208 kb
Host smart-ad0ecf16-a415-4093-b1a6-91d3479a024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185203615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3185203615
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1868854228
Short name T780
Test name
Test status
Simulation time 106377256 ps
CPU time 2.32 seconds
Started Jun 07 08:32:44 PM PDT 24
Finished Jun 07 08:32:55 PM PDT 24
Peak memory 218224 kb
Host smart-e5c556f7-06ab-48ad-b0e0-770c1f9630fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868854228 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1868854228
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1328763212
Short name T665
Test name
Test status
Simulation time 53961269806 ps
CPU time 1195.74 seconds
Started Jun 07 08:32:54 PM PDT 24
Finished Jun 07 08:52:55 PM PDT 24
Peak memory 220944 kb
Host smart-d5dd3e06-09f6-401e-83f8-0a4ccba58ca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328763212 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1328763212
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.120171409
Short name T587
Test name
Test status
Simulation time 52215269 ps
CPU time 0.85 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:57 PM PDT 24
Peak memory 218440 kb
Host smart-aafd5fdf-ccc9-4be6-987a-44d41071ee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120171409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.120171409
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1138828004
Short name T576
Test name
Test status
Simulation time 29536709 ps
CPU time 1.43 seconds
Started Jun 07 08:33:43 PM PDT 24
Finished Jun 07 08:33:47 PM PDT 24
Peak memory 217280 kb
Host smart-49e9f23f-563c-4a3a-843a-34034b34d963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138828004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1138828004
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1228927887
Short name T137
Test name
Test status
Simulation time 24022430 ps
CPU time 1.25 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 229724 kb
Host smart-a36e0114-87f2-46ac-84dd-0881d81972e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228927887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1228927887
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2228756000
Short name T312
Test name
Test status
Simulation time 42497222 ps
CPU time 1.71 seconds
Started Jun 07 08:34:06 PM PDT 24
Finished Jun 07 08:34:13 PM PDT 24
Peak memory 218308 kb
Host smart-7dcaa4a6-ea1d-4446-80f5-73ce1705e6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228756000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2228756000
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2803014670
Short name T191
Test name
Test status
Simulation time 34335876 ps
CPU time 0.87 seconds
Started Jun 07 08:33:35 PM PDT 24
Finished Jun 07 08:33:41 PM PDT 24
Peak memory 219356 kb
Host smart-e431ff39-3f89-400e-8fca-e1fb06bb9e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803014670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2803014670
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.3797894323
Short name T420
Test name
Test status
Simulation time 53855021 ps
CPU time 0.83 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:57 PM PDT 24
Peak memory 218176 kb
Host smart-ffafcc12-6a32-4189-b8b2-3822f5a58256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797894323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3797894323
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2047043255
Short name T697
Test name
Test status
Simulation time 82598565 ps
CPU time 1.16 seconds
Started Jun 07 08:34:03 PM PDT 24
Finished Jun 07 08:34:10 PM PDT 24
Peak memory 216932 kb
Host smart-92f065d9-c3c8-474c-98f6-4af12a306443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047043255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2047043255
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3389687048
Short name T189
Test name
Test status
Simulation time 44548263 ps
CPU time 1.19 seconds
Started Jun 07 08:33:46 PM PDT 24
Finished Jun 07 08:33:49 PM PDT 24
Peak memory 225620 kb
Host smart-bab5a8b2-9da9-4023-b680-0c2f053af2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389687048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3389687048
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3577556656
Short name T517
Test name
Test status
Simulation time 47369046 ps
CPU time 1.12 seconds
Started Jun 07 08:33:47 PM PDT 24
Finished Jun 07 08:33:50 PM PDT 24
Peak memory 219080 kb
Host smart-35222a48-7e84-4853-b568-28f8980ad9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577556656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3577556656
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.490288703
Short name T580
Test name
Test status
Simulation time 32975716 ps
CPU time 1.22 seconds
Started Jun 07 08:33:59 PM PDT 24
Finished Jun 07 08:34:06 PM PDT 24
Peak memory 224040 kb
Host smart-0e79a895-023e-4b23-8c97-cf366d6cc81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490288703 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.490288703
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1058436527
Short name T666
Test name
Test status
Simulation time 101072834 ps
CPU time 1.6 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:05 PM PDT 24
Peak memory 218312 kb
Host smart-9457ebfe-f912-4101-94b9-753b799f5c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058436527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1058436527
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3512726763
Short name T797
Test name
Test status
Simulation time 24299618 ps
CPU time 1.04 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 224032 kb
Host smart-18942126-6f2d-43ad-bb83-5ab7ceaba989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512726763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3512726763
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1119051150
Short name T813
Test name
Test status
Simulation time 38549842 ps
CPU time 1.35 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 216924 kb
Host smart-e7fdb9c0-4f79-4fcd-9704-97e9446e9369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119051150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1119051150
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.1749195143
Short name T799
Test name
Test status
Simulation time 20615337 ps
CPU time 1.19 seconds
Started Jun 07 08:33:56 PM PDT 24
Finished Jun 07 08:34:02 PM PDT 24
Peak memory 229640 kb
Host smart-cff1ba1c-b69d-47ae-bbe2-1c796c7732c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749195143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1749195143
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1866085381
Short name T332
Test name
Test status
Simulation time 101719000 ps
CPU time 1.85 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 218292 kb
Host smart-62619bda-ad86-423a-99c2-1c1372cfebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866085381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1866085381
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2986203741
Short name T159
Test name
Test status
Simulation time 104518826 ps
CPU time 1.02 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:58 PM PDT 24
Peak memory 223852 kb
Host smart-bc3f2553-8a99-47a7-9008-e0f01e926a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986203741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2986203741
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2785983526
Short name T647
Test name
Test status
Simulation time 36836827 ps
CPU time 1.43 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 218156 kb
Host smart-fa97a95c-8dd9-4e43-ab7b-cf1120ea44e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785983526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2785983526
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1352483922
Short name T662
Test name
Test status
Simulation time 24648065 ps
CPU time 1.04 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 224028 kb
Host smart-7e0a482e-1cec-45c3-a19b-f5b251d616a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352483922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1352483922
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3592509036
Short name T574
Test name
Test status
Simulation time 50389810 ps
CPU time 1.47 seconds
Started Jun 07 08:33:49 PM PDT 24
Finished Jun 07 08:33:52 PM PDT 24
Peak memory 217072 kb
Host smart-024c509b-341c-420a-89c7-08323d6235f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592509036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3592509036
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.1904833700
Short name T782
Test name
Test status
Simulation time 20995399 ps
CPU time 0.97 seconds
Started Jun 07 08:32:36 PM PDT 24
Finished Jun 07 08:32:48 PM PDT 24
Peak memory 215096 kb
Host smart-c9b3a2f1-14f5-4d65-b5e2-3a741ad4324c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904833700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1904833700
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.202359586
Short name T755
Test name
Test status
Simulation time 27030830 ps
CPU time 0.92 seconds
Started Jun 07 08:32:38 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 216148 kb
Host smart-7b03c702-d9c2-4527-a06d-b544707b81c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202359586 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.202359586
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1326153107
Short name T482
Test name
Test status
Simulation time 26435682 ps
CPU time 1.11 seconds
Started Jun 07 08:32:44 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 219420 kb
Host smart-b66e83d8-e07f-4499-8919-e8bc51c1b721
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326153107 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1326153107
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.216301269
Short name T670
Test name
Test status
Simulation time 52710067 ps
CPU time 0.97 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 219492 kb
Host smart-e5d14bfa-eb49-4a80-9e11-48c0912ea72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216301269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.216301269
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2973163522
Short name T613
Test name
Test status
Simulation time 72540168 ps
CPU time 1.39 seconds
Started Jun 07 08:32:51 PM PDT 24
Finished Jun 07 08:32:57 PM PDT 24
Peak memory 219420 kb
Host smart-ce0499a9-5dae-4ee6-b31d-663991aa32b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973163522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2973163522
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1595804374
Short name T511
Test name
Test status
Simulation time 25613489 ps
CPU time 0.96 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 215488 kb
Host smart-57b776ef-f4ab-41b2-8d04-8833524e431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595804374 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1595804374
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.358387301
Short name T509
Test name
Test status
Simulation time 62139874 ps
CPU time 0.98 seconds
Started Jun 07 08:32:38 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 207004 kb
Host smart-1eb5ad3b-7934-4c98-89f3-b88fabed28e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358387301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.358387301
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2422520877
Short name T657
Test name
Test status
Simulation time 66222525 ps
CPU time 0.89 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 215200 kb
Host smart-d3d1e52b-6dc4-4f85-a03b-eb9e105c1da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422520877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2422520877
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.478329429
Short name T452
Test name
Test status
Simulation time 295183692 ps
CPU time 5.89 seconds
Started Jun 07 08:32:42 PM PDT 24
Finished Jun 07 08:32:57 PM PDT 24
Peak memory 215188 kb
Host smart-45d8d800-8075-4cbc-bdf3-1d12aeb090f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478329429 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.478329429
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3897791781
Short name T442
Test name
Test status
Simulation time 14055252372 ps
CPU time 317.75 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:38:17 PM PDT 24
Peak memory 221376 kb
Host smart-6541cdf2-dead-4daf-9b48-d2c96b4beabb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897791781 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3897791781
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3549041982
Short name T158
Test name
Test status
Simulation time 46333405 ps
CPU time 1.11 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:57 PM PDT 24
Peak memory 219492 kb
Host smart-2e55ac55-d98b-458c-ad37-87c8eb92b891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549041982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3549041982
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2932078696
Short name T664
Test name
Test status
Simulation time 118806745 ps
CPU time 2.78 seconds
Started Jun 07 08:33:35 PM PDT 24
Finished Jun 07 08:33:44 PM PDT 24
Peak memory 217204 kb
Host smart-5beaedb1-811e-498c-b9aa-6a8073f5c1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932078696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2932078696
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2184960151
Short name T790
Test name
Test status
Simulation time 21292629 ps
CPU time 0.97 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 215312 kb
Host smart-dcb48718-1249-45bb-b345-8d88bdf9fc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184960151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2184960151
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2875237991
Short name T802
Test name
Test status
Simulation time 47732999 ps
CPU time 1.25 seconds
Started Jun 07 08:33:44 PM PDT 24
Finished Jun 07 08:33:47 PM PDT 24
Peak memory 219592 kb
Host smart-cb12c191-8782-4add-a601-353a093aab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875237991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2875237991
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.4000702659
Short name T356
Test name
Test status
Simulation time 62184974 ps
CPU time 0.95 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 218288 kb
Host smart-b017b6d7-0557-45ba-a520-bfcb4a958c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000702659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.4000702659
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.757966917
Short name T563
Test name
Test status
Simulation time 45161270 ps
CPU time 1.31 seconds
Started Jun 07 08:33:42 PM PDT 24
Finished Jun 07 08:33:46 PM PDT 24
Peak memory 218520 kb
Host smart-127cf83b-3a39-49a8-80ac-164d75c5caa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757966917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.757966917
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3126811425
Short name T550
Test name
Test status
Simulation time 38035242 ps
CPU time 1.1 seconds
Started Jun 07 08:33:43 PM PDT 24
Finished Jun 07 08:33:46 PM PDT 24
Peak memory 220560 kb
Host smart-fda37552-fc53-4844-9e82-a41f190ee404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126811425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3126811425
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1971213953
Short name T342
Test name
Test status
Simulation time 28185472 ps
CPU time 1.11 seconds
Started Jun 07 08:33:49 PM PDT 24
Finished Jun 07 08:33:52 PM PDT 24
Peak memory 218052 kb
Host smart-c6187b88-ce5b-463d-b03b-ba22ce9d7bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971213953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1971213953
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2146163049
Short name T841
Test name
Test status
Simulation time 25420133 ps
CPU time 1.15 seconds
Started Jun 07 08:33:59 PM PDT 24
Finished Jun 07 08:34:07 PM PDT 24
Peak memory 220472 kb
Host smart-ba084624-dc61-4739-829c-19ce29215e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146163049 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2146163049
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1679266979
Short name T307
Test name
Test status
Simulation time 73974939 ps
CPU time 1.17 seconds
Started Jun 07 08:34:01 PM PDT 24
Finished Jun 07 08:34:08 PM PDT 24
Peak memory 215092 kb
Host smart-e68323ad-b36c-41de-9ab9-6d7d2f909599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679266979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1679266979
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.4211759724
Short name T5
Test name
Test status
Simulation time 21857917 ps
CPU time 1.01 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 218720 kb
Host smart-daec3115-cc7c-478a-9fd1-bb9f1b8f6938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211759724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4211759724
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1476469471
Short name T338
Test name
Test status
Simulation time 83733652 ps
CPU time 2.84 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:13 PM PDT 24
Peak memory 219884 kb
Host smart-80b7be6e-5303-44ef-9786-cade37bd7cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476469471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1476469471
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3529822014
Short name T130
Test name
Test status
Simulation time 24089123 ps
CPU time 1.25 seconds
Started Jun 07 08:33:40 PM PDT 24
Finished Jun 07 08:33:45 PM PDT 24
Peak memory 229620 kb
Host smart-a59140c8-c7a9-4d86-b09c-812bc542468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529822014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3529822014
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1442967645
Short name T297
Test name
Test status
Simulation time 108379925 ps
CPU time 1.43 seconds
Started Jun 07 08:33:59 PM PDT 24
Finished Jun 07 08:34:06 PM PDT 24
Peak memory 218436 kb
Host smart-82ed7182-7e92-4ab5-9b6f-ecc9f946c37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442967645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1442967645
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3245730367
Short name T135
Test name
Test status
Simulation time 56928326 ps
CPU time 1.01 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:57 PM PDT 24
Peak memory 220444 kb
Host smart-3d7dcdbb-4766-4f38-a6f6-34d9aba64868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245730367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3245730367
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3759387390
Short name T536
Test name
Test status
Simulation time 38542586 ps
CPU time 1.38 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 216996 kb
Host smart-fc0fdfd9-8eb0-49a9-9561-e8aac604f3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759387390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3759387390
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3995414375
Short name T559
Test name
Test status
Simulation time 22740715 ps
CPU time 1.01 seconds
Started Jun 07 08:34:08 PM PDT 24
Finished Jun 07 08:34:14 PM PDT 24
Peak memory 218580 kb
Host smart-702bd984-fa63-4ed1-b334-b64a4ceeae96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995414375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3995414375
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3368437928
Short name T616
Test name
Test status
Simulation time 39012602 ps
CPU time 1.4 seconds
Started Jun 07 08:33:49 PM PDT 24
Finished Jun 07 08:33:52 PM PDT 24
Peak memory 219368 kb
Host smart-61671856-de9a-48be-8ae8-264ebc333028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368437928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3368437928
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2572511976
Short name T60
Test name
Test status
Simulation time 39080106 ps
CPU time 1.11 seconds
Started Jun 07 08:34:03 PM PDT 24
Finished Jun 07 08:34:10 PM PDT 24
Peak memory 224000 kb
Host smart-1364f444-0b9e-4bfb-bfa2-696edc93f990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572511976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2572511976
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.311449646
Short name T650
Test name
Test status
Simulation time 50778860 ps
CPU time 1.71 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 218248 kb
Host smart-ac46ce94-f977-404e-8af1-b31cc14d45a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311449646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.311449646
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3388632805
Short name T122
Test name
Test status
Simulation time 29557727 ps
CPU time 1.24 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 219084 kb
Host smart-410f413b-a0a1-43a3-9a4c-0e7c3973455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388632805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3388632805
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2448767841
Short name T394
Test name
Test status
Simulation time 58887528 ps
CPU time 0.98 seconds
Started Jun 07 08:32:38 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 206564 kb
Host smart-0f54477f-1cb3-4d78-818a-dbd0a060e1ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448767841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2448767841
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3983475066
Short name T202
Test name
Test status
Simulation time 16107347 ps
CPU time 0.88 seconds
Started Jun 07 08:32:45 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 216228 kb
Host smart-438315e5-a672-496d-b3e4-7692a8598f2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983475066 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3983475066
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3459952378
Short name T78
Test name
Test status
Simulation time 63516460 ps
CPU time 1.16 seconds
Started Jun 07 08:32:56 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 216684 kb
Host smart-44f7b7d2-bff8-4d19-8ae9-1ab72522026d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459952378 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3459952378
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1903519728
Short name T123
Test name
Test status
Simulation time 35053951 ps
CPU time 0.94 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:33:00 PM PDT 24
Peak memory 219600 kb
Host smart-50dbb34d-0d98-4455-a6ae-96a6e95e4770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903519728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1903519728
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.4268822806
Short name T481
Test name
Test status
Simulation time 46047128 ps
CPU time 1.12 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 216932 kb
Host smart-c7c58e93-169a-42fa-b2ad-3cf64b6fe819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268822806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4268822806
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2432506531
Short name T528
Test name
Test status
Simulation time 21448346 ps
CPU time 1.13 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 215476 kb
Host smart-b937d3d4-be29-4695-a2dc-ba6dbcd31683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432506531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2432506531
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3371730672
Short name T606
Test name
Test status
Simulation time 17468421 ps
CPU time 1.02 seconds
Started Jun 07 08:32:50 PM PDT 24
Finished Jun 07 08:32:57 PM PDT 24
Peak memory 207032 kb
Host smart-e7c1379f-ff7b-44e6-96de-2daed3950d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371730672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3371730672
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3142747616
Short name T564
Test name
Test status
Simulation time 49459988 ps
CPU time 0.92 seconds
Started Jun 07 08:32:52 PM PDT 24
Finished Jun 07 08:32:58 PM PDT 24
Peak memory 215204 kb
Host smart-23a3f726-5e99-4ddd-b83f-2465853f5ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142747616 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3142747616
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.568949650
Short name T677
Test name
Test status
Simulation time 325446224 ps
CPU time 3.39 seconds
Started Jun 07 08:32:48 PM PDT 24
Finished Jun 07 08:32:57 PM PDT 24
Peak memory 216976 kb
Host smart-2088234c-3436-484a-b3e6-cc387c29abf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568949650 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.568949650
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3627503794
Short name T208
Test name
Test status
Simulation time 27819119414 ps
CPU time 594 seconds
Started Jun 07 08:32:38 PM PDT 24
Finished Jun 07 08:42:43 PM PDT 24
Peak memory 217988 kb
Host smart-d5ff138c-43d3-402c-a4dd-aa037744d14e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627503794 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3627503794
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3960293997
Short name T133
Test name
Test status
Simulation time 32260575 ps
CPU time 0.9 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 218464 kb
Host smart-c2698ff8-9045-4428-ab07-962bcbef6408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960293997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3960293997
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.195902392
Short name T527
Test name
Test status
Simulation time 36957619 ps
CPU time 1.12 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 218456 kb
Host smart-25a69a96-3907-4b50-a3d6-0d738f54b9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195902392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.195902392
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2706935433
Short name T141
Test name
Test status
Simulation time 58930158 ps
CPU time 1.05 seconds
Started Jun 07 08:33:55 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 219544 kb
Host smart-c45908a2-af8f-41d2-8275-fc5678a65a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706935433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2706935433
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1275727940
Short name T507
Test name
Test status
Simulation time 114822627 ps
CPU time 1.33 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 218296 kb
Host smart-e9797319-996a-43df-99ab-c8cc8bba7a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275727940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1275727940
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2406912349
Short name T809
Test name
Test status
Simulation time 73272272 ps
CPU time 1.16 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:34:00 PM PDT 24
Peak memory 225328 kb
Host smart-f3af527f-fd94-4142-ae63-1a68d739a37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406912349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2406912349
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.4007177920
Short name T488
Test name
Test status
Simulation time 88947322 ps
CPU time 2.15 seconds
Started Jun 07 08:33:50 PM PDT 24
Finished Jun 07 08:33:55 PM PDT 24
Peak memory 219756 kb
Host smart-57f973fc-541c-4666-94ba-b35375309ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007177920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4007177920
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2188417910
Short name T739
Test name
Test status
Simulation time 20339752 ps
CPU time 1.15 seconds
Started Jun 07 08:34:00 PM PDT 24
Finished Jun 07 08:34:07 PM PDT 24
Peak memory 219508 kb
Host smart-2fe16af4-dfd9-46bc-8f41-81d0ba88922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188417910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2188417910
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.683897576
Short name T512
Test name
Test status
Simulation time 54994478 ps
CPU time 1.58 seconds
Started Jun 07 08:34:02 PM PDT 24
Finished Jun 07 08:34:10 PM PDT 24
Peak memory 217944 kb
Host smart-09d3b5e1-e33a-4e5c-9129-95ce04a55b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683897576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.683897576
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_genbits.3792111416
Short name T425
Test name
Test status
Simulation time 49668300 ps
CPU time 1.25 seconds
Started Jun 07 08:33:55 PM PDT 24
Finished Jun 07 08:34:01 PM PDT 24
Peak memory 218224 kb
Host smart-6e73bb13-562f-469a-b816-e1aa82da8b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792111416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3792111416
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.619332220
Short name T62
Test name
Test status
Simulation time 25405679 ps
CPU time 1.04 seconds
Started Jun 07 08:34:02 PM PDT 24
Finished Jun 07 08:34:09 PM PDT 24
Peak memory 223996 kb
Host smart-e6c3f1e9-8520-41b8-9e13-00d60e8c6ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619332220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.619332220
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.655660767
Short name T311
Test name
Test status
Simulation time 9129520555 ps
CPU time 120.74 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:36:10 PM PDT 24
Peak memory 217388 kb
Host smart-f5dfde97-372e-49d4-8e36-8e6387b34874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655660767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.655660767
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3463594636
Short name T701
Test name
Test status
Simulation time 47835076 ps
CPU time 1.04 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 224072 kb
Host smart-b9707070-8990-483c-999e-d58ddfb0bd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463594636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3463594636
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2418801034
Short name T519
Test name
Test status
Simulation time 54766764 ps
CPU time 1.35 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 217992 kb
Host smart-46fa9dbb-a487-4e6b-9f2a-cb74c02ed35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418801034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2418801034
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3135424906
Short name T469
Test name
Test status
Simulation time 30750001 ps
CPU time 1.27 seconds
Started Jun 07 08:34:10 PM PDT 24
Finished Jun 07 08:34:17 PM PDT 24
Peak memory 219776 kb
Host smart-976ed457-8c7a-4f4e-bd99-44e4be919afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135424906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3135424906
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1612874416
Short name T695
Test name
Test status
Simulation time 29224514 ps
CPU time 1.25 seconds
Started Jun 07 08:34:02 PM PDT 24
Finished Jun 07 08:34:09 PM PDT 24
Peak memory 218364 kb
Host smart-089ce0a5-c13b-4d24-808e-a09f95af73cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612874416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1612874416
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2686909565
Short name T57
Test name
Test status
Simulation time 29071856 ps
CPU time 1.33 seconds
Started Jun 07 08:34:00 PM PDT 24
Finished Jun 07 08:34:08 PM PDT 24
Peak memory 225644 kb
Host smart-f265f247-7123-44df-a39e-eea8a2e8e9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686909565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2686909565
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2728307555
Short name T847
Test name
Test status
Simulation time 58162116 ps
CPU time 1.22 seconds
Started Jun 07 08:33:55 PM PDT 24
Finished Jun 07 08:34:01 PM PDT 24
Peak memory 217976 kb
Host smart-d0f00962-e667-420a-8f83-840f651bbae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728307555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2728307555
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2921978075
Short name T194
Test name
Test status
Simulation time 43124713 ps
CPU time 1.26 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 233948 kb
Host smart-7044e9c2-bb32-4e60-a7a6-070133e640fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921978075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2921978075
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3766245938
Short name T694
Test name
Test status
Simulation time 92316721 ps
CPU time 1.26 seconds
Started Jun 07 08:33:49 PM PDT 24
Finished Jun 07 08:33:52 PM PDT 24
Peak memory 218612 kb
Host smart-db834c4d-bf57-424a-80ed-1043d0d1e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766245938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3766245938
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert_test.670835677
Short name T460
Test name
Test status
Simulation time 74267798 ps
CPU time 0.89 seconds
Started Jun 07 08:33:16 PM PDT 24
Finished Jun 07 08:33:20 PM PDT 24
Peak memory 214492 kb
Host smart-d135077d-acdf-46f0-af0a-92ebf776a307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670835677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.670835677
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3849487839
Short name T743
Test name
Test status
Simulation time 15221904 ps
CPU time 0.89 seconds
Started Jun 07 08:32:56 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 216336 kb
Host smart-c68d623b-adb9-480b-80f2-f0678e8e227f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849487839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3849487839
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2410240497
Short name T735
Test name
Test status
Simulation time 23237666 ps
CPU time 1.01 seconds
Started Jun 07 08:33:02 PM PDT 24
Finished Jun 07 08:33:06 PM PDT 24
Peak memory 217996 kb
Host smart-6ae7544d-12a0-41d5-9f2c-ea521cbb7319
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410240497 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2410240497
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2024841272
Short name T541
Test name
Test status
Simulation time 24217839 ps
CPU time 0.94 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 218588 kb
Host smart-ac42e5e5-a551-4b96-a2b0-030385b28151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024841272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2024841272
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.721279437
Short name T453
Test name
Test status
Simulation time 54468992 ps
CPU time 1.2 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:33:00 PM PDT 24
Peak memory 216768 kb
Host smart-2c323462-eb4e-4c6f-8dc6-db27b1a9ef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721279437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.721279437
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1180281433
Short name T91
Test name
Test status
Simulation time 22668896 ps
CPU time 0.96 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 215904 kb
Host smart-d6c5b892-8fff-4457-ac5b-41cbed1fcf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180281433 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1180281433
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3100472644
Short name T25
Test name
Test status
Simulation time 14704933 ps
CPU time 0.93 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 207004 kb
Host smart-1928e371-3649-43db-a8f1-a2f98abe9184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100472644 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3100472644
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1873536088
Short name T601
Test name
Test status
Simulation time 21673660 ps
CPU time 0.92 seconds
Started Jun 07 08:32:38 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 215228 kb
Host smart-6e04e6bc-d14a-44ab-a90e-ceff28cea127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873536088 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1873536088
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.847754425
Short name T712
Test name
Test status
Simulation time 211612934 ps
CPU time 2.53 seconds
Started Jun 07 08:32:49 PM PDT 24
Finished Jun 07 08:32:57 PM PDT 24
Peak memory 215216 kb
Host smart-962e2f44-27a7-4ef0-9428-bc237862beda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847754425 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.847754425
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3388145746
Short name T775
Test name
Test status
Simulation time 180217059892 ps
CPU time 2008.63 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 09:06:29 PM PDT 24
Peak memory 226528 kb
Host smart-22f74abf-371c-4cf3-b73c-c4fb99ebf9c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388145746 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3388145746
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3582087067
Short name T125
Test name
Test status
Simulation time 24987117 ps
CPU time 1.18 seconds
Started Jun 07 08:34:00 PM PDT 24
Finished Jun 07 08:34:07 PM PDT 24
Peak memory 219732 kb
Host smart-2d19ca57-5570-48d1-846c-e353a49d5806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582087067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3582087067
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3797434948
Short name T388
Test name
Test status
Simulation time 38362787 ps
CPU time 1.15 seconds
Started Jun 07 08:34:00 PM PDT 24
Finished Jun 07 08:34:07 PM PDT 24
Peak memory 219476 kb
Host smart-95c12656-20e1-4c8e-ba5e-882a86cd6d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797434948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3797434948
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.84855347
Short name T131
Test name
Test status
Simulation time 29130763 ps
CPU time 0.98 seconds
Started Jun 07 08:33:48 PM PDT 24
Finished Jun 07 08:33:51 PM PDT 24
Peak memory 219560 kb
Host smart-f7c45da1-5fff-442a-87f9-4b952f804188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84855347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.84855347
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.4148111461
Short name T292
Test name
Test status
Simulation time 80002997 ps
CPU time 1.28 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 217288 kb
Host smart-712a672e-bfc8-4bbc-9b5b-67287a46fbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148111461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4148111461
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1254704153
Short name T439
Test name
Test status
Simulation time 24183751 ps
CPU time 1.11 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 224032 kb
Host smart-49c1c7bb-9e03-443e-9511-bee9703a09a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254704153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1254704153
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1011697068
Short name T779
Test name
Test status
Simulation time 75208922 ps
CPU time 2.54 seconds
Started Jun 07 08:33:52 PM PDT 24
Finished Jun 07 08:33:56 PM PDT 24
Peak memory 219944 kb
Host smart-0843a299-05c2-44da-936b-ef0618ed1e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011697068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1011697068
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.715074535
Short name T572
Test name
Test status
Simulation time 19836516 ps
CPU time 1.04 seconds
Started Jun 07 08:33:59 PM PDT 24
Finished Jun 07 08:34:05 PM PDT 24
Peak memory 218424 kb
Host smart-fade2810-ab54-43fe-80ae-d5d724051714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715074535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.715074535
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.174610653
Short name T411
Test name
Test status
Simulation time 62929140 ps
CPU time 1.25 seconds
Started Jun 07 08:33:54 PM PDT 24
Finished Jun 07 08:34:00 PM PDT 24
Peak memory 216892 kb
Host smart-a0203863-b084-49c4-9399-0fe387ea707d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174610653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.174610653
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.995435831
Short name T136
Test name
Test status
Simulation time 23689596 ps
CPU time 1.35 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 229692 kb
Host smart-6a9a2e69-b506-4b78-b35b-fe9a80020c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995435831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.995435831
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3039597333
Short name T368
Test name
Test status
Simulation time 41970501 ps
CPU time 1.57 seconds
Started Jun 07 08:33:49 PM PDT 24
Finished Jun 07 08:33:53 PM PDT 24
Peak memory 217200 kb
Host smart-1489fdf5-cb46-41bc-8a5e-12f848774778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039597333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3039597333
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2611441880
Short name T170
Test name
Test status
Simulation time 26169648 ps
CPU time 0.99 seconds
Started Jun 07 08:33:51 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 223848 kb
Host smart-bf1eadc8-9a2e-4fca-ba83-55e50f31f6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611441880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2611441880
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.4048942684
Short name T79
Test name
Test status
Simulation time 139982520 ps
CPU time 1.51 seconds
Started Jun 07 08:33:50 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 219740 kb
Host smart-5988b6c5-3384-453b-9e23-340d3e7deba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048942684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.4048942684
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.963078290
Short name T165
Test name
Test status
Simulation time 20197148 ps
CPU time 1.19 seconds
Started Jun 07 08:34:06 PM PDT 24
Finished Jun 07 08:34:12 PM PDT 24
Peak memory 224004 kb
Host smart-d801ffda-9679-4ece-8db1-387910b4258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963078290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.963078290
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2682621528
Short name T395
Test name
Test status
Simulation time 63580430 ps
CPU time 0.9 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 216964 kb
Host smart-ec872d80-c02d-4551-a99e-5f2bbcd42192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682621528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2682621528
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1752408202
Short name T154
Test name
Test status
Simulation time 19846521 ps
CPU time 1.2 seconds
Started Jun 07 08:33:46 PM PDT 24
Finished Jun 07 08:33:49 PM PDT 24
Peak memory 224048 kb
Host smart-d0384cd0-1e46-442c-a64e-80a1770a251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752408202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1752408202
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3021242562
Short name T649
Test name
Test status
Simulation time 48455178 ps
CPU time 1.51 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 216932 kb
Host smart-4637622f-5695-4222-8aa6-b467d0295397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021242562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3021242562
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.431275989
Short name T192
Test name
Test status
Simulation time 163298733 ps
CPU time 1.04 seconds
Started Jun 07 08:33:50 PM PDT 24
Finished Jun 07 08:33:53 PM PDT 24
Peak memory 220644 kb
Host smart-893bfb1d-ea2c-4819-bbb5-d0ea0e8083a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431275989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.431275989
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2583514853
Short name T458
Test name
Test status
Simulation time 56635493 ps
CPU time 1.24 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 216948 kb
Host smart-f8c3615d-87b8-43fe-875b-9de19fbac8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583514853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2583514853
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3989016958
Short name T61
Test name
Test status
Simulation time 36911186 ps
CPU time 1.14 seconds
Started Jun 07 08:34:06 PM PDT 24
Finished Jun 07 08:34:12 PM PDT 24
Peak memory 232248 kb
Host smart-664901e4-8ac2-41a1-981e-9038ea5cebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989016958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3989016958
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.95640155
Short name T728
Test name
Test status
Simulation time 123524828 ps
CPU time 1.22 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 216824 kb
Host smart-d2bb9744-f81a-495a-b999-37b937b67b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95640155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.95640155
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.3686690985
Short name T346
Test name
Test status
Simulation time 19053112 ps
CPU time 0.97 seconds
Started Jun 07 08:33:00 PM PDT 24
Finished Jun 07 08:33:05 PM PDT 24
Peak memory 215084 kb
Host smart-e396fd12-09dd-43f2-bec1-b826f4800eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686690985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3686690985
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.285349286
Short name T369
Test name
Test status
Simulation time 26904392 ps
CPU time 1.21 seconds
Started Jun 07 08:33:00 PM PDT 24
Finished Jun 07 08:33:05 PM PDT 24
Peak memory 218004 kb
Host smart-c82cbf95-ebb1-402c-964a-340b644084cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285349286 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.285349286
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3533584805
Short name T690
Test name
Test status
Simulation time 21459671 ps
CPU time 0.96 seconds
Started Jun 07 08:32:55 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 218624 kb
Host smart-06447ee3-5c0e-4fe2-9c98-1218838854bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533584805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3533584805
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.66734782
Short name T748
Test name
Test status
Simulation time 132446430 ps
CPU time 2.65 seconds
Started Jun 07 08:32:49 PM PDT 24
Finished Jun 07 08:32:58 PM PDT 24
Peak memory 218212 kb
Host smart-aea8f5fd-c65b-482c-9378-1e0ab08c27d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66734782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.66734782
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2240261824
Short name T539
Test name
Test status
Simulation time 20382978 ps
CPU time 1.08 seconds
Started Jun 07 08:33:02 PM PDT 24
Finished Jun 07 08:33:06 PM PDT 24
Peak memory 215892 kb
Host smart-5026e04c-f120-4223-a709-317f440fe3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240261824 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2240261824
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.594041326
Short name T276
Test name
Test status
Simulation time 19594908 ps
CPU time 1.02 seconds
Started Jun 07 08:33:06 PM PDT 24
Finished Jun 07 08:33:11 PM PDT 24
Peak memory 206996 kb
Host smart-cd48f2f2-b3c4-4b6c-92e3-2ecb16a6b8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594041326 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.594041326
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2306100871
Short name T444
Test name
Test status
Simulation time 35364001 ps
CPU time 0.94 seconds
Started Jun 07 08:32:52 PM PDT 24
Finished Jun 07 08:32:58 PM PDT 24
Peak memory 215092 kb
Host smart-daa66f5b-33b2-4f98-a71d-01e05a6cf6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306100871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2306100871
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2799171492
Short name T620
Test name
Test status
Simulation time 174263372 ps
CPU time 1.63 seconds
Started Jun 07 08:33:01 PM PDT 24
Finished Jun 07 08:33:06 PM PDT 24
Peak memory 216784 kb
Host smart-7db7d99a-66ae-4ac3-b711-a46e61a557c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799171492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2799171492
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.531274665
Short name T669
Test name
Test status
Simulation time 83601334080 ps
CPU time 813.26 seconds
Started Jun 07 08:33:01 PM PDT 24
Finished Jun 07 08:46:38 PM PDT 24
Peak memory 223556 kb
Host smart-500980d1-f88b-45e3-b3fe-9b59c523c764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531274665 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.531274665
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2229884446
Short name T184
Test name
Test status
Simulation time 33062352 ps
CPU time 0.93 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 218592 kb
Host smart-97e3523f-970d-4875-a418-8fe7549f9974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229884446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2229884446
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3514876477
Short name T733
Test name
Test status
Simulation time 82882622 ps
CPU time 2.87 seconds
Started Jun 07 08:34:09 PM PDT 24
Finished Jun 07 08:34:18 PM PDT 24
Peak memory 219792 kb
Host smart-21af6a36-b65a-43a5-b264-9a66be9f1bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514876477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3514876477
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3401285538
Short name T773
Test name
Test status
Simulation time 59994115 ps
CPU time 1.16 seconds
Started Jun 07 08:33:57 PM PDT 24
Finished Jun 07 08:34:04 PM PDT 24
Peak memory 232280 kb
Host smart-b057187b-d395-47d4-acd1-72c56e9e5d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401285538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3401285538
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2637555376
Short name T454
Test name
Test status
Simulation time 97597226 ps
CPU time 1.67 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 218376 kb
Host smart-da102d24-16fd-4209-8f2d-123e5f3ff4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637555376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2637555376
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1480016172
Short name T760
Test name
Test status
Simulation time 22459281 ps
CPU time 0.95 seconds
Started Jun 07 08:34:05 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 218668 kb
Host smart-ebc20836-cad9-49e7-a280-53e46cdea0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480016172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1480016172
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2123494910
Short name T77
Test name
Test status
Simulation time 167204604 ps
CPU time 1.4 seconds
Started Jun 07 08:34:03 PM PDT 24
Finished Jun 07 08:34:10 PM PDT 24
Peak memory 217120 kb
Host smart-bd6c00eb-6ff6-4a24-9295-cb2f3488378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123494910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2123494910
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3374104421
Short name T6
Test name
Test status
Simulation time 20560858 ps
CPU time 1.16 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 219728 kb
Host smart-a05e12e8-7b64-4203-b8fa-29264aca8f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374104421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3374104421
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2064138196
Short name T475
Test name
Test status
Simulation time 100603699 ps
CPU time 1.24 seconds
Started Jun 07 08:34:05 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 218444 kb
Host smart-17f56896-389e-4788-bc91-ea6f5db6ed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064138196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2064138196
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1863862665
Short name T72
Test name
Test status
Simulation time 66305967 ps
CPU time 1.01 seconds
Started Jun 07 08:34:05 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 219468 kb
Host smart-9d1f49dc-05b8-40e2-bf47-3275e6c2d8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863862665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1863862665
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1524665286
Short name T767
Test name
Test status
Simulation time 97559109 ps
CPU time 1.29 seconds
Started Jun 07 08:34:04 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 218200 kb
Host smart-3046e7bc-50b5-4cc7-8be4-1c62d1507a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524665286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1524665286
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1403451030
Short name T717
Test name
Test status
Simulation time 93997322 ps
CPU time 0.99 seconds
Started Jun 07 08:34:14 PM PDT 24
Finished Jun 07 08:34:26 PM PDT 24
Peak memory 219880 kb
Host smart-72cd4010-72a1-4ad7-a564-32a9276bea65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403451030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1403451030
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.176441063
Short name T324
Test name
Test status
Simulation time 88250387 ps
CPU time 1.11 seconds
Started Jun 07 08:33:53 PM PDT 24
Finished Jun 07 08:33:58 PM PDT 24
Peak memory 216768 kb
Host smart-d5361c77-3a8c-4aca-bc8c-a6c42cd3f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176441063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.176441063
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3527131625
Short name T195
Test name
Test status
Simulation time 25931495 ps
CPU time 1.15 seconds
Started Jun 07 08:34:13 PM PDT 24
Finished Jun 07 08:34:21 PM PDT 24
Peak memory 219716 kb
Host smart-983a24fd-7e78-4fce-beb4-74ed536df221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527131625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3527131625
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3517007941
Short name T508
Test name
Test status
Simulation time 61146795 ps
CPU time 2.13 seconds
Started Jun 07 08:34:03 PM PDT 24
Finished Jun 07 08:34:11 PM PDT 24
Peak memory 218108 kb
Host smart-97082ac2-cc80-48c1-89c6-325a549a7e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517007941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3517007941
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2219452850
Short name T175
Test name
Test status
Simulation time 26048829 ps
CPU time 1.13 seconds
Started Jun 07 08:33:58 PM PDT 24
Finished Jun 07 08:34:05 PM PDT 24
Peak memory 218368 kb
Host smart-f634ac51-c151-4187-b0b3-a49316648d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219452850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2219452850
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1583505621
Short name T561
Test name
Test status
Simulation time 63470213 ps
CPU time 1.31 seconds
Started Jun 07 08:34:08 PM PDT 24
Finished Jun 07 08:34:15 PM PDT 24
Peak memory 218072 kb
Host smart-7468becd-d4d6-4b2c-981c-7bebc35ceade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583505621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1583505621
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1753199200
Short name T682
Test name
Test status
Simulation time 31940521 ps
CPU time 1.1 seconds
Started Jun 07 08:33:56 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 229636 kb
Host smart-04c34693-96fa-41de-b5fa-75847662bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753199200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1753199200
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1266967420
Short name T306
Test name
Test status
Simulation time 78111239 ps
CPU time 1.46 seconds
Started Jun 07 08:34:02 PM PDT 24
Finished Jun 07 08:34:09 PM PDT 24
Peak memory 219728 kb
Host smart-80e5a895-4b94-4b6d-866e-ee6a3a7c7ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266967420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1266967420
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.605107371
Short name T793
Test name
Test status
Simulation time 37446386 ps
CPU time 0.9 seconds
Started Jun 07 08:34:11 PM PDT 24
Finished Jun 07 08:34:17 PM PDT 24
Peak memory 219176 kb
Host smart-d903da31-d5d6-4ad3-b133-f9c39eaff137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605107371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.605107371
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1974908320
Short name T381
Test name
Test status
Simulation time 62181135 ps
CPU time 2.12 seconds
Started Jun 07 08:34:07 PM PDT 24
Finished Jun 07 08:34:15 PM PDT 24
Peak memory 219848 kb
Host smart-2f6249bb-f418-4fa5-879a-a55f4fd0644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974908320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1974908320
Directory /workspace/99.edn_genbits/latest
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