Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	147	1			T22	1		T27	1		T28	1
auto_req_mode	138	1			T1	1		T8	1		T12	1
sw_mode	2772	1			T4	60		T19	5		T20	42

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

316

1

T1

1

T8

1

T22

1

single

84

1

T27

1

T39

1

T12

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1523	1			T22	1		T27	1		T28	1
auto[2]	69	1			T4	60		T261	1		T262	1
auto[3]	195	1			T89	55		T263	1		T264	1
auto[4]	88	1			T8	1		T197	19		T265	1
auto[5]	52	1			T46	1		T266	1		T267	43
auto[6]	164	1			T71	1		T268	1		T269	1
auto[7]	966	1			T1	1		T19	5		T20	42

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[2]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	86	1			T22	1		T27	1		T28	1
auto[1]	auto_req_mode	82	1			T63	1		T40	1		T15	1
auto[1]	sw_mode	1355	1			T81	6		T64	1		T37	32
auto[2]	auto_req_mode	5	1			T261	1		T262	1		T270	1
auto[2]	sw_mode	64	1			T4	60		T271	1		T272	1
auto[3]	boot_req_mode	8	1			T273	1		T274	1		T275	1
auto[3]	auto_req_mode	2	1			T263	1		T264	1		-	-
auto[3]	sw_mode	185	1			T89	55		T276	1		T277	1
auto[4]	boot_req_mode	2	1			T278	1		T279	1		-	-
auto[4]	auto_req_mode	5	1			T8	1		T280	1		T281	1
auto[4]	sw_mode	81	1			T197	19		T265	1		T282	1
auto[5]	boot_req_mode	3	1			T266	1		T283	1		T284	1
auto[5]	auto_req_mode	2	1			T285	1		T286	1		-	-
auto[5]	sw_mode	47	1			T46	1		T267	43		T287	1
auto[6]	boot_req_mode	3	1			T288	1		T289	1		T290	1
auto[6]	auto_req_mode	6	1			T268	1		T291	1		T292	1
auto[6]	sw_mode	155	1			T71	1		T269	1		T244	63
auto[7]	boot_req_mode	45	1			T48	1		T49	1		T45	1
auto[7]	auto_req_mode	36	1			T1	1		T12	1		T17	1
auto[7]	sw_mode	885	1			T19	5		T20	42		T23	12