Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 34 0 34 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 9 0 9 100.00 100 1 1 0
cr_instantiate_intended 9 0 9 100.00 100 1 1 0
cr_reseed_intended 8 0 8 100.00 100 1 1 0
cr_update_intended 2 0 2 100.00 100 1 1 0
cr_uninstantiate_intended 1 0 1 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 3949 1 T1 1 T2 1 T4 72
auto[RES] 930 1 T1 1 T4 12 T19 1
auto[GEN] 3783 1 T1 2 T2 1 T4 60
auto[UPD] 503 1 T4 11 T20 4 T23 2
auto[UNI] 3455 1 T1 2 T4 72 T19 8


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 4216 1 T1 5 T4 86 T19 11
no_cmd_data 8407 1 T1 1 T2 2 T4 141


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 11254 1 T1 4 T2 2 T4 227
reseed_cmd 440 1 T1 1 T8 1 T5 4
generate_cmd 401 1 T1 1 T8 1 T5 3
boot_gen_cmd 277 1 T22 1 T27 1 T28 1
boot_ins_cmd 251 1 T22 1 T27 1 T28 1


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 4022 1 T1 3 T4 63 T19 3
false 8601 1 T1 3 T2 2 T4 164


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1302 1 T1 1 T8 5 T22 1
one 2132 1 T1 1 T2 1 T4 25


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 10842 1 T1 2 T2 2 T4 227
boot_mode 614 1 T22 2 T27 2 T28 2
auto_mode 1167 1 T1 4 T8 4 T5 7


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 9 0 9 100.00
Automatically Generated Cross Bins 9 0 9 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 190 1 T1 1 T38 1 T45 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 110 1 T8 1 T18 1 T12 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 50 1 T254 1 T207 1 T306 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 118 1 T1 1 T5 2 T17 1
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 45 1 T8 1 T12 1 T17 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 79 1 T48 1 T49 1 T45 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 29 1 T63 1 T306 1 T6 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1494 1 T2 1 T4 25 T19 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 83 1 T5 1 T18 1 T29 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 9 0 9 100.00
Automatically Generated Cross Bins 9 0 9 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 802 1 T4 17 T19 1 T20 13
auto[INS] some_cmd_data true auto_mode sw_cmd_req 88 1 T1 1 T17 1 T63 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 746 1 T4 24 T19 5 T20 10
auto[INS] some_cmd_data false auto_mode sw_cmd_req 83 1 T8 1 T40 1 T15 1
auto[INS] no_cmd_data true sw_mode sw_cmd_req 184 1 T4 3 T20 3 T23 1
auto[INS] no_cmd_data true auto_mode sw_cmd_req 65 1 T18 1 T29 1 T15 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1678 1 T2 1 T4 28 T19 2
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 115 1 T22 1 T27 1 T29 1
auto[INS] no_cmd_data false auto_mode sw_cmd_req 52 1 T18 1 T12 1 T29 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 201 1 T4 5 T20 2 T23 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 117 1 T12 1 T40 1 T15 2
auto[RES] some_cmd_data false sw_mode sw_cmd_req 177 1 T4 6 T19 1 T20 3
auto[RES] some_cmd_data false auto_mode reseed_cmd 112 1 T1 1 T8 1 T5 2
auto[RES] no_cmd_data true sw_mode sw_cmd_req 46 1 T81 1 T90 1 T91 2
auto[RES] no_cmd_data true auto_mode reseed_cmd 27 1 T18 1 T17 1 T72 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 47 1 T4 1 T197 1 T199 1
auto[RES] no_cmd_data false auto_mode reseed_cmd 123 1 T5 2 T18 1 T29 1


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 370 1 T4 8 T20 3 T23 2
auto[UPD] no_cmd_data sw_mode sw_cmd_req 115 1 T4 3 T20 1 T37 3


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 1 0 1 100.00
Automatically Generated Cross Bins 1 0 1 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3435 1 T1 1 T4 72 T19 8


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 288 1 T1 1 T8 1 T18 2
auto[RES] auto_mode sw_cmd_req 19 1 T17 1 T63 1 T207 1
auto[GEN] auto_mode sw_cmd_req 100 1 T8 1 T18 2 T29 2
auto[UPD] auto_mode sw_cmd_req 18 1 T72 1 T306 1 T74 1
auto[UNI] auto_mode sw_cmd_req 20 1 T1 1 T12 1 T307 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%