Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2498	1			T1	6		T4	47		T19	6
non_zero_bins[1]	1826	1			T1	1		T4	39		T19	5
zero	8413	1			T1	1		T2	2		T4	141

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	485	1			T4	11		T20	4		T23	2
uni	3542	1			T1	1		T4	72		T19	8
gen	3917	1			T1	4		T2	1		T4	60
res	800	1			T1	2		T4	12		T19	1
ins	3993	1			T1	1		T2	1		T4	72

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8530

1

T1

6

T2

2

T4

164

mubi_true

4207

1

T1

2

T4

63

T19

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

5

1

T128

1

T102

1

T132

1

pass

12732

1

T1

8

T2

2

T4

227

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	114	1			T4	2		T37	1		T49	1
upd	non_zero_bins[0]	pass	mubi_true	120	1			T4	3		T20	2		T23	1
upd	non_zero_bins[1]	pass	mubi_false	61	1			T4	1		T20	1		T23	1
upd	non_zero_bins[1]	pass	mubi_true	75	1			T4	2		T62	1		T254	1
upd	zero	pass	mubi_false	58	1			T4	2		T20	1		T37	2
upd	zero	pass	mubi_true	57	1			T4	1		T37	1		T62	1
uni	zero	pass	mubi_false	2584	1			T1	1		T4	55		T19	7
uni	zero	pass	mubi_true	958	1			T4	17		T19	1		T20	18
gen	non_zero_bins[0]	pass	mubi_false	472	1			T1	3		T4	7		T19	3
gen	non_zero_bins[0]	pass	mubi_true	443	1			T1	1		T4	6		T20	2
gen	non_zero_bins[1]	pass	mubi_false	347	1			T4	8		T20	4		T40	3
gen	non_zero_bins[1]	pass	mubi_true	373	1			T4	5		T19	1		T20	4
gen	zero	fail	mubi_false	3	1			T128	1		T102	1		T103	1
gen	zero	pass	mubi_false	1807	1			T2	1		T4	30		T19	1
gen	zero	pass	mubi_true	472	1			T4	4		T20	3		T22	2
res	non_zero_bins[0]	pass	mubi_false	168	1			T1	2		T4	3		T20	3
res	non_zero_bins[0]	pass	mubi_true	217	1			T4	5		T20	1		T23	1
res	non_zero_bins[1]	pass	mubi_false	125	1			T4	3		T19	1		T89	2
res	non_zero_bins[1]	pass	mubi_true	123	1			T20	1		T37	2		T48	1
res	zero	fail	mubi_false	2	1			T132	1		T133	1		-	-
res	zero	pass	mubi_false	90	1			T4	1		T63	2		T197	1
res	zero	pass	mubi_true	75	1			T17	2		T81	1		T72	2
ins	non_zero_bins[0]	pass	mubi_false	463	1			T4	11		T19	2		T20	5
ins	non_zero_bins[0]	pass	mubi_true	501	1			T4	10		T19	1		T20	8
ins	non_zero_bins[1]	pass	mubi_false	352	1			T4	13		T19	3		T20	5
ins	non_zero_bins[1]	pass	mubi_true	370	1			T1	1		T4	7		T20	5
ins	zero	pass	mubi_false	1884	1			T2	1		T4	28		T19	2
ins	zero	pass	mubi_true	423	1			T4	3		T20	3		T23	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded