SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[0].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[1].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[2].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[3].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[4].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[5].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[6].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1686 | 1 | T22 | 1 | T9 | 1 | T4 | 34 | ||||
auto[2] | 72165 | 1 | T22 | 4 | T9 | 16 | T4 | 136 | ||||
auto[3] | 71080 | 1 | T22 | 4 | T9 | 16 | T4 | 136 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 162 | 1 | T24 | 1 | T41 | 1 | T44 | 1 | ||||
auto[2] | 7261 | 1 | T24 | 38 | T5 | 1 | T41 | 4 | ||||
auto[3] | 7252 | 1 | T24 | 38 | T41 | 4 | T44 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 131 | 1 | T6 | 1 | T23 | 1 | T20 | 1 | ||||
auto[2] | 3315 | 1 | T6 | 22 | T23 | 4 | T20 | 56 | ||||
auto[3] | 3306 | 1 | T6 | 22 | T23 | 4 | T20 | 56 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 128 | 1 | T1 | 1 | T6 | 1 | T20 | 1 | ||||
auto[2] | 6180 | 1 | T1 | 50 | T2 | 1 | T6 | 38 | ||||
auto[3] | 6165 | 1 | T1 | 50 | T6 | 38 | T20 | 30 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 113 | 1 | T6 | 1 | T24 | 1 | T41 | 1 | ||||
auto[2] | 4854 | 1 | T6 | 34 | T24 | 4 | T41 | 4 | ||||
auto[3] | 4848 | 1 | T6 | 34 | T24 | 4 | T41 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 111 | 1 | T24 | 1 | T10 | 1 | T41 | 1 | ||||
auto[2] | 5325 | 1 | T24 | 47 | T10 | 364 | T41 | 4 | ||||
auto[3] | 5322 | 1 | T24 | 47 | T10 | 364 | T41 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 102 | 1 | T41 | 1 | T42 | 1 | T43 | 1 | ||||
auto[2] | 2957 | 1 | T41 | 6 | T42 | 56 | T43 | 60 | ||||
auto[3] | 2955 | 1 | T41 | 6 | T42 | 56 | T43 | 60 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |