Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	648042	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5184773

1

T1

27

T2

60

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1545789	1			T1	52		T2	5		T3	1
values[0x0]	1982105	1			T1	13		T2	36		T3	15
values[0x1]	2304921	1			T1	13		T2	27		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	320692	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5512123

1

T1

53

T2

61

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21841	1			T3	1		T9	1		T4	280
valid_sources[0x01]	21454	1			T2	2		T9	1		T4	318
valid_sources[0x02]	22812	1			T4	291		T39	606		T15	1
valid_sources[0x03]	23530	1			T2	1		T6	1		T9	1
valid_sources[0x04]	21365	1			T2	1		T4	258		T39	514
valid_sources[0x05]	20963	1			T2	2		T4	274		T19	1
valid_sources[0x06]	22413	1			T6	1		T9	1		T4	288
valid_sources[0x07]	23700	1			T4	283		T39	717		T15	1
valid_sources[0x08]	22388	1			T2	2		T6	3		T4	281
valid_sources[0x09]	21510	1			T4	272		T41	1		T39	497
valid_sources[0x0a]	23280	1			T6	2		T9	1		T4	279
valid_sources[0x0b]	25218	1			T3	1		T23	1		T4	318
valid_sources[0x0c]	22523	1			T9	2		T4	286		T39	644
valid_sources[0x0d]	23693	1			T9	2		T4	304		T39	584
valid_sources[0x0e]	22845	1			T1	4		T4	295		T19	1
valid_sources[0x0f]	22442	1			T9	3		T4	306		T39	460
valid_sources[0x10]	22436	1			T3	2		T4	219		T14	3
valid_sources[0x11]	21960	1			T2	1		T6	1		T4	254
valid_sources[0x12]	21849	1			T9	1		T4	261		T41	1
valid_sources[0x13]	22710	1			T6	1		T4	254		T39	659
valid_sources[0x14]	25287	1			T4	276		T41	1		T39	566
valid_sources[0x15]	22055	1			T4	274		T19	1		T41	1
valid_sources[0x16]	21877	1			T1	10		T9	3		T4	248
valid_sources[0x17]	22791	1			T6	2		T4	296		T69	4
valid_sources[0x18]	21859	1			T3	1		T6	1		T9	2
valid_sources[0x19]	22870	1			T6	1		T4	289		T41	1
valid_sources[0x1a]	21812	1			T2	1		T4	251		T41	1
valid_sources[0x1b]	22069	1			T2	2		T4	284		T19	1
valid_sources[0x1c]	23664	1			T2	1		T9	4		T4	286
valid_sources[0x1d]	22335	1			T6	2		T4	281		T41	2
valid_sources[0x1e]	21840	1			T6	1		T9	1		T4	260
valid_sources[0x1f]	22121	1			T1	1		T2	1		T4	307
valid_sources[0x20]	21346	1			T9	3		T4	249		T41	1
valid_sources[0x21]	23073	1			T6	1		T4	295		T39	630
valid_sources[0x22]	23136	1			T4	285		T39	526		T20	2
valid_sources[0x23]	21936	1			T4	293		T39	542		T20	5
valid_sources[0x24]	22037	1			T4	280		T19	1		T39	553
valid_sources[0x25]	23197	1			T4	292		T10	5		T19	1
valid_sources[0x26]	22982	1			T3	2		T4	283		T19	2
valid_sources[0x27]	22556	1			T4	309		T39	711		T15	1
valid_sources[0x28]	20782	1			T6	1		T4	315		T14	1
valid_sources[0x29]	21587	1			T4	299		T19	1		T41	1
valid_sources[0x2a]	23169	1			T4	283		T19	1		T41	1
valid_sources[0x2b]	23130	1			T4	267		T41	1		T39	545
valid_sources[0x2c]	22195	1			T2	1		T6	1		T9	2
valid_sources[0x2d]	24816	1			T4	287		T14	3		T39	692
valid_sources[0x2e]	20925	1			T6	1		T4	257		T19	1
valid_sources[0x2f]	22762	1			T6	1		T4	280		T19	1
valid_sources[0x30]	24285	1			T4	246		T41	1		T39	666
valid_sources[0x31]	22440	1			T9	2		T4	264		T41	1
valid_sources[0x32]	22068	1			T6	2		T4	266		T39	518
valid_sources[0x33]	23139	1			T6	1		T23	1		T4	275
valid_sources[0x34]	23246	1			T2	1		T4	256		T41	1
valid_sources[0x35]	22646	1			T2	1		T4	290		T41	1
valid_sources[0x36]	21799	1			T2	1		T4	258		T41	1
valid_sources[0x37]	22361	1			T6	1		T9	5		T4	284
valid_sources[0x38]	21236	1			T2	1		T4	277		T39	588
valid_sources[0x39]	24631	1			T2	1		T6	1		T9	1
valid_sources[0x3a]	21941	1			T6	1		T4	305		T19	2
valid_sources[0x3b]	21726	1			T6	1		T4	289		T39	546
valid_sources[0x3c]	22025	1			T1	4		T6	1		T4	269
valid_sources[0x3d]	23211	1			T6	1		T4	288		T41	1
valid_sources[0x3e]	21082	1			T4	244		T69	5		T41	1
valid_sources[0x3f]	23458	1			T4	287		T69	1		T39	548
valid_sources[0x40]	23852	1			T6	2		T9	2		T4	271
valid_sources[0x41]	21459	1			T6	1		T4	239		T69	3
valid_sources[0x42]	22642	1			T6	1		T4	317		T10	9
valid_sources[0x43]	21377	1			T4	296		T39	386		T42	1
valid_sources[0x44]	20691	1			T2	1		T4	256		T39	649
valid_sources[0x45]	21837	1			T1	3		T6	1		T4	286
valid_sources[0x46]	23272	1			T4	253		T19	3		T41	1
valid_sources[0x47]	21189	1			T3	2		T6	1		T4	272
valid_sources[0x48]	22910	1			T6	1		T9	1		T4	279
valid_sources[0x49]	24621	1			T2	5		T6	1		T4	265
valid_sources[0x4a]	21944	1			T4	317		T14	14		T39	587
valid_sources[0x4b]	22408	1			T1	2		T2	1		T4	283
valid_sources[0x4c]	23245	1			T2	1		T6	2		T9	1
valid_sources[0x4d]	22701	1			T9	2		T4	302		T39	383
valid_sources[0x4e]	20540	1			T6	5		T4	272		T10	2
valid_sources[0x4f]	23651	1			T4	295		T39	400		T43	2
valid_sources[0x50]	23482	1			T2	1		T4	281		T41	1
valid_sources[0x51]	23145	1			T4	251		T39	523		T70	5
valid_sources[0x52]	23258	1			T6	2		T4	290		T69	4
valid_sources[0x53]	24706	1			T6	2		T4	247		T10	1
valid_sources[0x54]	21643	1			T4	276		T39	461		T42	2
valid_sources[0x55]	23676	1			T6	1		T4	305		T5	18
valid_sources[0x56]	23269	1			T4	314		T14	1		T41	2
valid_sources[0x57]	23171	1			T2	1		T9	1		T4	285
valid_sources[0x58]	23147	1			T2	1		T6	1		T4	264
valid_sources[0x59]	24418	1			T6	1		T4	313		T69	4
valid_sources[0x5a]	22015	1			T2	1		T3	1		T6	1
valid_sources[0x5b]	23342	1			T4	260		T39	576		T46	1
valid_sources[0x5c]	23687	1			T9	2		T4	275		T19	1
valid_sources[0x5d]	23703	1			T3	3		T9	1		T4	316
valid_sources[0x5e]	19995	1			T4	323		T69	3		T19	1
valid_sources[0x5f]	24141	1			T6	1		T4	295		T39	573
valid_sources[0x60]	23316	1			T4	300		T19	2		T41	3
valid_sources[0x61]	24986	1			T4	281		T39	539		T44	138
valid_sources[0x62]	22124	1			T4	242		T39	672		T20	1
valid_sources[0x63]	23700	1			T6	1		T9	1		T4	312
valid_sources[0x64]	25168	1			T1	4		T4	256		T41	3
valid_sources[0x65]	23110	1			T4	332		T19	3		T39	553
valid_sources[0x66]	22484	1			T4	281		T41	1		T39	450
valid_sources[0x67]	21409	1			T9	1		T4	227		T19	2
valid_sources[0x68]	23235	1			T3	1		T6	1		T9	1
valid_sources[0x69]	22715	1			T4	291		T41	1		T39	614
valid_sources[0x6a]	23789	1			T2	2		T9	1		T4	274
valid_sources[0x6b]	23298	1			T2	1		T4	289		T39	421
valid_sources[0x6c]	23335	1			T1	1		T4	273		T39	490
valid_sources[0x6d]	23962	1			T3	1		T6	1		T4	259
valid_sources[0x6e]	23129	1			T4	290		T39	578		T28	2
valid_sources[0x6f]	22239	1			T6	3		T23	1		T4	290
valid_sources[0x70]	24654	1			T9	1		T4	275		T10	6
valid_sources[0x71]	21875	1			T6	1		T4	289		T39	613
valid_sources[0x72]	20765	1			T6	1		T4	272		T41	1
valid_sources[0x73]	21406	1			T6	2		T4	276		T14	12
valid_sources[0x74]	22998	1			T22	100		T9	1		T4	325
valid_sources[0x75]	22666	1			T2	1		T4	288		T19	2
valid_sources[0x76]	21930	1			T6	2		T4	286		T19	1
valid_sources[0x77]	21731	1			T4	269		T41	1		T39	350
valid_sources[0x78]	23940	1			T6	1		T4	230		T39	488
valid_sources[0x79]	21279	1			T4	281		T10	4		T39	559
valid_sources[0x7a]	23173	1			T4	260		T10	25		T19	1
valid_sources[0x7b]	21984	1			T9	5		T4	292		T39	478
valid_sources[0x7c]	23625	1			T6	1		T4	270		T14	10
valid_sources[0x7d]	22698	1			T3	1		T9	4		T4	297
valid_sources[0x7e]	22577	1			T24	124		T4	252		T19	1
valid_sources[0x7f]	24088	1			T2	1		T6	1		T4	303
valid_sources[0x80]	22595	1			T4	286		T10	6		T39	636

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1307805

1

T1

6

T2

2

T6

7

values[0x0]

all_enables

biggest_size

1940665

1

T1

12

T2

32

T3

6

values[0x1]

all_enables

biggest_size

1936303

1

T1

9

T2

26

T3

1