Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2516	1			T1	3		T24	1		T4	35
non_zero_bins[1]	1870	1			T6	2		T22	2		T24	1
zero	8436	1			T1	5		T6	2		T22	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	506	1			T6	1		T24	1		T4	13
uni	3585	1			T1	3		T6	1		T22	2
gen	3884	1			T1	2		T6	1		T22	1
res	826	1			T9	2		T4	9		T10	2
ins	4021	1			T1	3		T6	1		T22	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8644

1

T1

5

T6

3

T22

2

mubi_true

4178

1

T1

3

T6

1

T22

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

2

1

T147

1

T113

1

-

-

pass

12820

1

T1

8

T6

4

T22

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	112	1			T39	3		T47	1		T40	2
upd	non_zero_bins[0]	pass	mubi_true	111	1			T4	3		T39	1		T40	1
upd	non_zero_bins[1]	pass	mubi_false	84	1			T6	1		T24	1		T4	2
upd	non_zero_bins[1]	pass	mubi_true	93	1			T4	6		T42	1		T40	3
upd	zero	pass	mubi_false	48	1			T4	1		T39	1		T40	1
upd	zero	pass	mubi_true	58	1			T4	1		T39	2		T40	1
uni	zero	pass	mubi_false	2662	1			T1	2		T6	1		T22	1
uni	zero	pass	mubi_true	923	1			T1	1		T22	1		T4	27
gen	non_zero_bins[0]	pass	mubi_false	451	1			T1	1		T4	6		T14	3
gen	non_zero_bins[0]	pass	mubi_true	494	1			T4	7		T10	3		T39	9
gen	non_zero_bins[1]	pass	mubi_false	329	1			T22	1		T4	8		T10	1
gen	non_zero_bins[1]	pass	mubi_true	359	1			T4	4		T41	1		T39	6
gen	zero	fail	mubi_false	1	1			T113	1		-	-		-	-
gen	zero	pass	mubi_false	1818	1			T6	1		T23	2		T4	38
gen	zero	pass	mubi_true	432	1			T1	1		T24	1		T9	4
res	non_zero_bins[0]	pass	mubi_false	170	1			T4	2		T39	4		T44	1
res	non_zero_bins[0]	pass	mubi_true	193	1			T4	1		T14	2		T41	1
res	non_zero_bins[1]	pass	mubi_false	138	1			T4	5		T39	2		T20	2
res	non_zero_bins[1]	pass	mubi_true	144	1			T4	1		T10	2		T19	3
res	zero	fail	mubi_false	1	1			T147	1		-	-		-	-
res	zero	pass	mubi_false	91	1			T9	2		T39	3		T62	1
res	zero	pass	mubi_true	89	1			T39	2		T70	1		T68	1
ins	non_zero_bins[0]	pass	mubi_false	495	1			T1	1		T4	10		T39	10
ins	non_zero_bins[0]	pass	mubi_true	490	1			T1	1		T24	1		T4	6
ins	non_zero_bins[1]	pass	mubi_false	356	1			T9	1		T4	5		T10	1
ins	non_zero_bins[1]	pass	mubi_true	367	1			T6	1		T22	1		T4	9
ins	zero	pass	mubi_false	1888	1			T1	1		T23	2		T4	37
ins	zero	pass	mubi_true	425	1			T22	1		T4	7		T5	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded