Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	202396302	9245249	0	0
boot_gen_cmd_rd_A	202396302	51547	0	0
boot_ins_cmd_rd_A	202396302	59198	0	0
ctrl_rd_A	202396302	52404	0	0
err_code_test_rd_A	202396302	61040	0	0
intr_enable_rd_A	202396302	59824	0	0
max_num_reqs_between_reseeds_rd_A	202396302	53132	0	0
regwen_rd_A	202396302	59978	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202396302	9245249	0	0
T4	184609	106373	0	0
T5	1814	0	0	0
T7	1975	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T19	2783	0	0	0
T39	583860	217087	0	0
T40	0	69288	0	0
T41	2749	0	0	0
T44	1793	0	0	0
T62	0	99267	0	0
T69	1519	0	0	0
T212	0	188446	0	0
T213	0	419726	0	0
T214	0	617058	0	0
T215	0	132887	0	0
T216	0	88987	0	0
T217	0	201458	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202396302	51547	0	0
T15	458	0	0	0
T20	2992	0	0	0
T28	2436	0	0	0
T39	583860	3330	0	0
T42	2759	0	0	0
T44	1793	0	0	0
T46	2688	0	0	0
T50	973	0	0	0
T70	1404	0	0	0
T88	3398	0	0	0
T217	0	5573	0	0
T218	0	2598	0	0
T219	0	2963	0	0
T220	0	1398	0	0
T221	0	2431	0	0
T222	0	1677	0	0
T223	0	7104	0	0
T224	0	4334	0	0
T225	0	5624	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202396302	59198	0	0
T15	458	0	0	0
T20	2992	0	0	0
T28	2436	0	0	0
T39	583860	3470	0	0
T42	2759	0	0	0
T44	1793	0	0	0
T46	2688	0	0	0
T50	973	0	0	0
T70	1404	0	0	0
T88	3398	0	0	0
T217	0	6592	0	0
T218	0	2933	0	0
T219	0	3700	0	0
T220	0	1571	0	0
T221	0	2673	0	0
T222	0	1672	0	0
T223	0	7997	0	0
T224	0	4906	0	0
T225	0	6482	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202396302	52404	0	0
T15	458	0	0	0
T20	2992	0	0	0
T25	0	2	0	0
T27	0	8	0	0
T28	2436	0	0	0
T39	583860	3379	0	0
T42	2759	0	0	0
T44	1793	0	0	0
T46	2688	0	0	0
T50	973	0	0	0
T68	0	3	0	0
T70	1404	0	0	0
T79	0	1	0	0
T88	3398	0	0	0
T201	0	4	0	0
T217	0	6049	0	0
T218	0	2542	0	0
T226	0	1	0	0
T227	0	9	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202396302	61040	0	0
T15	458	0	0	0
T20	2992	0	0	0
T28	2436	0	0	0
T39	583860	3659	0	0
T42	2759	0	0	0
T44	1793	0	0	0
T46	2688	0	0	0
T50	973	0	0	0
T70	1404	0	0	0
T88	3398	0	0	0
T217	0	7013	0	0
T218	0	3083	0	0
T219	0	3958	0	0
T220	0	1836	0	0
T221	0	2775	0	0
T222	0	1725	0	0
T223	0	8141	0	0
T224	0	5055	0	0
T225	0	6659	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202396302	59824	0	0
T15	458	0	0	0
T20	2992	0	0	0
T28	2436	0	0	0
T39	583860	3857	0	0
T42	2759	0	0	0
T44	1793	0	0	0
T46	2688	0	0	0
T50	973	0	0	0
T68	0	76	0	0
T70	1404	0	0	0
T88	3398	0	0	0
T217	0	6209	0	0
T218	0	3185	0	0
T219	0	3482	0	0
T220	0	1651	0	0
T221	0	2729	0	0
T227	0	46	0	0
T228	0	52	0	0
T229	0	49	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202396302	53132	0	0
T15	458	0	0	0
T20	2992	0	0	0
T28	2436	0	0	0
T39	583860	3554	0	0
T42	2759	0	0	0
T44	1793	0	0	0
T46	2688	0	0	0
T50	973	0	0	0
T70	1404	0	0	0
T88	3398	0	0	0
T217	0	5846	0	0
T218	0	2470	0	0
T219	0	3245	0	0
T220	0	1487	0	0
T221	0	2315	0	0
T222	0	1503	0	0
T223	0	7344	0	0
T224	0	4173	0	0
T225	0	5599	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202396302	59978	0	0
T15	458	0	0	0
T20	2992	0	0	0
T28	2436	0	0	0
T39	583860	3780	0	0
T42	2759	0	0	0
T44	1793	0	0	0
T46	2688	0	0	0
T50	973	0	0	0
T70	1404	0	0	0
T88	3398	0	0	0
T217	0	6510	0	0
T218	0	3059	0	0
T219	0	3700	0	0
T220	0	1649	0	0
T221	0	2669	0	0
T222	0	1857	0	0
T223	0	7765	0	0
T224	0	4988	0	0
T225	0	6441	0	0