Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T23,T5,T77
1	1	Covered	T1,T23,T5

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T22
1	0	Covered	T2,T19,T7
1	1	Covered	T2,T9,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T31,T29
1	0	Covered	T2,T5,T7

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T28,T31,T29
1	Covered	T2,T5,T7

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T28,T31,T29
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T5,T7
1	Covered	T2,T5,T7

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T5

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T9,T10,T14
AutoCaptGenCnt	143	Covered	T9,T10,T14
AutoCaptReseedCnt	141	Covered	T9,T10,T14
AutoDispatch	125	Covered	T9,T10,T14
AutoFirstAckWait	119	Covered	T9,T10,T14
AutoLoadIns	69	Covered	T2,T9,T10
AutoSendGenCmd	150	Covered	T9,T10,T14
AutoSendReseedCmd	162	Covered	T9,T10,T14
BootDone	98	Covered	T1,T23,T5
BootGenAckWait	90	Covered	T1,T23,T5
BootInsAckWait	80	Covered	T1,T23,T5
BootLoadGen	85	Covered	T1,T23,T5
BootLoadIns	65	Covered	T1,T23,T5
BootLoadUni	102	Covered	T1,T44,T46
BootPulse	94	Covered	T1,T23,T5
BootUniAckWait	107	Covered	T1,T44,T46
Error	188	Covered	T2,T5,T7
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T28,T31,T29
SWPortMode	74	Covered	T1,T6,T22

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T9,T10,T14
AutoAckWait->Error	188	Covered	T109,T110
AutoAckWait->Idle	211	Covered	T19,T66,T85
AutoAckWait->RejectCsrngEntropy	188	Covered	T111,T112,T113
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T9,T10,T14
AutoCaptGenCnt->Error	188	Covered	T114,T115,T116
AutoCaptGenCnt->Idle	211	Covered	T117,T118,T119
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T28,T98,T120
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T9,T10,T14
AutoCaptReseedCnt->Error	188	Not Covered
AutoCaptReseedCnt->Idle	211	Covered	T85,T121,T122
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T123,T124,T125
AutoDispatch->AutoCaptGenCnt	143	Covered	T9,T10,T14
AutoDispatch->AutoCaptReseedCnt	141	Covered	T9,T10,T14
AutoDispatch->Error	188	Covered	T126,T127,T128
AutoDispatch->Idle	138	Covered	T9,T10,T14
AutoDispatch->RejectCsrngEntropy	188	Covered	T102,T129
AutoFirstAckWait->AutoDispatch	125	Covered	T9,T10,T14
AutoFirstAckWait->Error	188	Covered	T7,T92,T130
AutoFirstAckWait->Idle	211	Covered	T131,T132,T133
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T100,T134,T135
AutoLoadIns->AutoFirstAckWait	119	Covered	T9,T10,T14
AutoLoadIns->Error	188	Covered	T2,T54,T136
AutoLoadIns->Idle	211	Covered	T2,T7,T8
AutoLoadIns->RejectCsrngEntropy	188	Covered	T103
AutoSendGenCmd->AutoAckWait	156	Covered	T9,T10,T14
AutoSendGenCmd->Error	188	Covered	T137
AutoSendGenCmd->Idle	211	Covered	T66,T138,T139
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T140,T141
AutoSendReseedCmd->AutoAckWait	168	Covered	T9,T10,T14
AutoSendReseedCmd->Error	188	Covered	T56,T142
AutoSendReseedCmd->Idle	211	Covered	T143,T144,T145
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T146,T147
BootDone->BootLoadUni	102	Covered	T1,T44,T46
BootDone->Error	188	Covered	T148,T149,T150
BootDone->Idle	211	Covered	T23,T77,T151
BootDone->RejectCsrngEntropy	188	Covered	T152,T153,T154
BootGenAckWait->BootPulse	94	Covered	T1,T23,T5
BootGenAckWait->Error	188	Covered	T155,T156
BootGenAckWait->Idle	211	Covered	T148,T157,T158
BootGenAckWait->RejectCsrngEntropy	188	Covered	T159,T160
BootInsAckWait->BootLoadGen	85	Covered	T1,T23,T5
BootInsAckWait->Error	188	Covered	T5,T51,T151
BootInsAckWait->Idle	211	Covered	T5,T78,T72
BootInsAckWait->RejectCsrngEntropy	188	Covered	T105
BootLoadGen->BootGenAckWait	90	Covered	T1,T23,T5
BootLoadGen->Error	188	Covered	T161
BootLoadGen->Idle	211	Covered	T80,T162,T163
BootLoadGen->RejectCsrngEntropy	188	Covered	T164,T104,T165
BootLoadIns->BootInsAckWait	80	Covered	T1,T23,T5
BootLoadIns->Error	188	Covered	T166,T167,T168
BootLoadIns->Idle	211	Covered	T81,T169
BootLoadIns->RejectCsrngEntropy	188	Covered	T99,T106,T170
BootLoadUni->BootUniAckWait	107	Covered	T1,T44,T46
BootLoadUni->Error	188	Covered	T171,T172
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T30,T101,T173
BootPulse->BootDone	98	Covered	T1,T23,T5
BootPulse->Error	188	Covered	T174
BootPulse->Idle	211	Covered	T175,T176,T177
BootPulse->RejectCsrngEntropy	188	Covered	T178,T179,T180
BootUniAckWait->Error	188	Covered	T181,T182
BootUniAckWait->Idle	112	Covered	T1,T44,T46
BootUniAckWait->RejectCsrngEntropy	188	Covered	T29,T183,T184
Idle->AutoLoadIns	69	Covered	T2,T9,T10
Idle->BootLoadIns	65	Covered	T1,T23,T5
Idle->Error	188	Covered	T16,T17,T18
Idle->RejectCsrngEntropy	188	Covered	T30,T98,T99
Idle->SWPortMode	74	Covered	T1,T6,T22
RejectCsrngEntropy->Error	188	Covered	T31,T49,T185
RejectCsrngEntropy->Idle	211	Covered	T28,T29,T30
SWPortMode->Error	188	Covered	T15,T16,T52
SWPortMode->Idle	211	Covered	T4,T39,T28
SWPortMode->RejectCsrngEntropy	188	Covered	T28,T31,T29

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T5
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T22
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T5
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T5
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T5
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T5
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T5
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T5
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T5
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T44,T46
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T23,T5,T77
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T44,T46
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T44,T46
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T44,T46
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T10,T14
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T10,T14
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T10,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T9,T10,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T14
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T22
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T31,T29
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T72,T16,T8

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T2,T5,T7
1	0	1	-	Not Covered
1	0	0	-	Covered	T28,T31,T29
0	-	-	1	Covered	T2,T23,T5
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	201967009	140546	0	0
FpvSecCmErrorStEscalate_A	201967009	141712	0	0
u_state_regs_A	201925252	201746887	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	140546	0	0
T2	2535	511	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	364	0	0
T6	4843	0	0	0
T7	0	1070	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	218	0	0
T16	0	14372	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	370	0	0
T49	0	440	0	0
T51	0	414	0	0
T52	0	1151	0	0
T72	0	1060	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	141712	0	0
T2	2535	512	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	365	0	0
T6	4843	0	0	0
T7	0	1071	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	219	0	0
T16	0	14632	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	371	0	0
T49	0	441	0	0
T51	0	415	0	0
T52	0	1152	0	0
T72	0	1061	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201925252	201746887	0	0
T1	2612	2546	0	0
T2	1284	1125	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0