Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T5

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T22,T23
DataWait	75	Covered	T6,T22,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T2,T5,T7
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T176,T177,T186
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T22,T23
DataWait->AckPls	80	Covered	T6,T22,T23
DataWait->Disabled	107	Covered	T78,T80,T117
DataWait->Error	99	Covered	T5,T8,T151
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T81,T187,T188
EndPointClear->Error	99	Covered	T16,T189,T190
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T22,T23
Idle->Disabled	107	Covered	T2,T23,T4
Idle->Error	99	Covered	T2,T5,T7

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T22,T23
Idle	-	1	0	-	Covered	T6,T22,T23
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T22,T23
DataWait	-	-	-	0	Covered	T6,T22,T23
AckPls	-	-	-	-	Covered	T6,T22,T23
Error	-	-	-	-	Covered	T2,T5,T7
default	-	-	-	-	Covered	T7,T31,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1413769063	995372	0	0
FpvSecCmErrorStEscalate_A	1413769063	1003534	0	0
u_state_regs_A	1413727306	1412478751	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1413769063	995372	0	0
T2	17745	3577	0	0
T3	12173	0	0	0
T4	1292263	0	0	0
T5	0	2548	0	0
T6	33901	0	0	0
T7	0	7440	0	0
T9	11445	0	0	0
T10	47397	0	0	0
T14	53235	0	0	0
T15	0	1526	0	0
T16	0	100604	0	0
T22	14924	0	0	0
T23	7189	0	0	0
T24	16884	0	0	0
T31	0	2540	0	0
T49	0	3030	0	0
T51	0	2898	0	0
T52	0	8057	0	0
T72	0	7770	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1413769063	1003534	0	0
T2	17745	3584	0	0
T3	12173	0	0	0
T4	1292263	0	0	0
T5	0	2555	0	0
T6	33901	0	0	0
T7	0	7447	0	0
T9	11445	0	0	0
T10	47397	0	0	0
T14	53235	0	0	0
T15	0	1533	0	0
T16	0	102424	0	0
T22	14924	0	0	0
T23	7189	0	0	0
T24	16884	0	0	0
T31	0	2547	0	0
T49	0	3037	0	0
T51	0	2905	0	0
T52	0	8064	0	0
T72	0	7777	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1413727306	1412478751	0	0
T1	18284	17822	0	0
T2	16494	15381	0	0
T3	12173	11676	0	0
T4	1292263	1292179	0	0
T6	33901	33313	0	0
T9	11445	11025	0	0
T10	47397	46781	0	0
T22	14924	14273	0	0
T23	7189	6573	0	0
T24	16884	16394	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T9,T4
DataWait	75	Covered	T22,T9,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T2,T5,T7
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T9,T4
DataWait->AckPls	80	Covered	T22,T9,T4
DataWait->Disabled	107	Covered	T117,T191,T192
DataWait->Error	99	Covered	T8,T157,T54
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T81,T187,T188
EndPointClear->Error	99	Covered	T16,T189,T190
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T22,T9,T4
Idle->Disabled	107	Covered	T2,T23,T4
Idle->Error	99	Covered	T2,T5,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T22,T9,T4
Idle	-	1	0	-	Covered	T22,T9,T4
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T22,T9,T4
DataWait	-	-	-	0	Covered	T22,T9,T4
AckPls	-	-	-	-	Covered	T22,T9,T4
Error	-	-	-	-	Covered	T2,T5,T7
default	-	-	-	-	Covered	T7,T31,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	201967009	140096	0	0
FpvSecCmErrorStEscalate_A	201967009	141262	0	0
u_state_regs_A	201925252	201746887	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	140096	0	0
T2	2535	511	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	364	0	0
T6	4843	0	0	0
T7	0	1020	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	218	0	0
T16	0	14372	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	320	0	0
T49	0	390	0	0
T51	0	414	0	0
T52	0	1151	0	0
T72	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	141262	0	0
T2	2535	512	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	365	0	0
T6	4843	0	0	0
T7	0	1021	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	219	0	0
T16	0	14632	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	321	0	0
T49	0	391	0	0
T51	0	415	0	0
T52	0	1152	0	0
T72	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201925252	201746887	0	0
T1	2612	2546	0	0
T2	1284	1125	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T41,T44
DataWait	75	Covered	T24,T5,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T2,T5,T7
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T41,T44
DataWait->AckPls	80	Covered	T24,T41,T44
DataWait->Disabled	107	Covered	T193,T138,T139
DataWait->Error	99	Covered	T5,T151,T92
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T81,T187,T188
EndPointClear->Error	99	Covered	T16,T189,T190
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T24,T5,T41
Idle->Disabled	107	Covered	T2,T23,T4
Idle->Error	99	Covered	T2,T7,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T24,T41,T44
Idle	-	1	0	-	Covered	T24,T5,T41
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T24,T41,T44
DataWait	-	-	-	0	Covered	T24,T5,T41
AckPls	-	-	-	-	Covered	T24,T41,T44
Error	-	-	-	-	Covered	T2,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	201967009	142546	0	0
FpvSecCmErrorStEscalate_A	201967009	143712	0	0
u_state_regs_A	201967009	201788644	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	142546	0	0
T2	2535	511	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	364	0	0
T6	4843	0	0	0
T7	0	1070	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	218	0	0
T16	0	14372	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	370	0	0
T49	0	440	0	0
T51	0	414	0	0
T52	0	1151	0	0
T72	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	143712	0	0
T2	2535	512	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	365	0	0
T6	4843	0	0	0
T7	0	1071	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	219	0	0
T16	0	14632	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	371	0	0
T49	0	441	0	0
T51	0	415	0	0
T52	0	1152	0	0
T72	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T6,T20
DataWait	75	Covered	T1,T2,T6
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T2,T5,T7
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T6,T20
DataWait->AckPls	80	Covered	T1,T6,T20
DataWait->Disabled	107	Covered	T78,T80,T194
DataWait->Error	99	Covered	T2,T72,T52
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T81,T187,T188
EndPointClear->Error	99	Covered	T16,T189,T190
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T1,T2,T6
Idle->Disabled	107	Covered	T2,T23,T4
Idle->Error	99	Covered	T5,T7,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T1,T6,T20
Idle	-	1	0	-	Covered	T1,T2,T6
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T1,T6,T20
DataWait	-	-	-	0	Covered	T1,T2,T6
AckPls	-	-	-	-	Covered	T1,T6,T20
Error	-	-	-	-	Covered	T2,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	201967009	142546	0	0
FpvSecCmErrorStEscalate_A	201967009	143712	0	0
u_state_regs_A	201967009	201788644	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	142546	0	0
T2	2535	511	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	364	0	0
T6	4843	0	0	0
T7	0	1070	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	218	0	0
T16	0	14372	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	370	0	0
T49	0	440	0	0
T51	0	414	0	0
T52	0	1151	0	0
T72	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	143712	0	0
T2	2535	512	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	365	0	0
T6	4843	0	0	0
T7	0	1071	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	219	0	0
T16	0	14632	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	371	0	0
T49	0	441	0	0
T51	0	415	0	0
T52	0	1152	0	0
T72	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T24,T41
DataWait	75	Covered	T6,T24,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T2,T5,T7
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T24,T41
DataWait->AckPls	80	Covered	T6,T24,T41
DataWait->Disabled	107	Covered	T195,T118,T196
DataWait->Error	99	Covered	T109,T130,T174
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T81,T187,T188
EndPointClear->Error	99	Covered	T16,T189,T190
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T24,T41
Idle->Disabled	107	Covered	T2,T23,T4
Idle->Error	99	Covered	T2,T5,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T24,T41
Idle	-	1	0	-	Covered	T6,T24,T41
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T24,T41
DataWait	-	-	-	0	Covered	T6,T24,T41
AckPls	-	-	-	-	Covered	T6,T24,T41
Error	-	-	-	-	Covered	T2,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	201967009	142546	0	0
FpvSecCmErrorStEscalate_A	201967009	143712	0	0
u_state_regs_A	201967009	201788644	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	142546	0	0
T2	2535	511	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	364	0	0
T6	4843	0	0	0
T7	0	1070	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	218	0	0
T16	0	14372	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	370	0	0
T49	0	440	0	0
T51	0	414	0	0
T52	0	1151	0	0
T72	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	143712	0	0
T2	2535	512	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	365	0	0
T6	4843	0	0	0
T7	0	1071	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	219	0	0
T16	0	14632	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	371	0	0
T49	0	441	0	0
T51	0	415	0	0
T52	0	1152	0	0
T72	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T10,T41
DataWait	75	Covered	T24,T10,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T2,T5,T7
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T10,T41
DataWait->AckPls	80	Covered	T24,T10,T41
DataWait->Disabled	107	Covered	T197,T198
DataWait->Error	99	Covered	T126,T199
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T81,T187,T188
EndPointClear->Error	99	Covered	T16,T189,T190
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T24,T10,T41
Idle->Disabled	107	Covered	T2,T23,T4
Idle->Error	99	Covered	T2,T5,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T24,T10,T41
Idle	-	1	0	-	Covered	T24,T10,T41
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T24,T10,T41
DataWait	-	-	-	0	Covered	T24,T10,T41
AckPls	-	-	-	-	Covered	T24,T10,T41
Error	-	-	-	-	Covered	T2,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	201967009	142546	0	0
FpvSecCmErrorStEscalate_A	201967009	143712	0	0
u_state_regs_A	201967009	201788644	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	142546	0	0
T2	2535	511	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	364	0	0
T6	4843	0	0	0
T7	0	1070	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	218	0	0
T16	0	14372	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	370	0	0
T49	0	440	0	0
T51	0	414	0	0
T52	0	1151	0	0
T72	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	143712	0	0
T2	2535	512	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	365	0	0
T6	4843	0	0	0
T7	0	1071	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	219	0	0
T16	0	14632	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	371	0	0
T49	0	441	0	0
T51	0	415	0	0
T52	0	1152	0	0
T72	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T23,T20
DataWait	75	Covered	T6,T23,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T2,T5,T7
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T200
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T23,T20
DataWait->AckPls	80	Covered	T6,T23,T20
DataWait->Disabled	107	Covered	T201,T202,T163
DataWait->Error	99	Covered	T171,T203,T150
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T81,T187,T188
EndPointClear->Error	99	Covered	T16,T189,T190
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T23,T20
Idle->Disabled	107	Covered	T2,T23,T4
Idle->Error	99	Covered	T2,T5,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T23,T20
Idle	-	1	0	-	Covered	T6,T23,T20
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T23,T20
DataWait	-	-	-	0	Covered	T6,T23,T20
AckPls	-	-	-	-	Covered	T6,T23,T20
Error	-	-	-	-	Covered	T2,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	201967009	142546	0	0
FpvSecCmErrorStEscalate_A	201967009	143712	0	0
u_state_regs_A	201967009	201788644	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	142546	0	0
T2	2535	511	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	364	0	0
T6	4843	0	0	0
T7	0	1070	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	218	0	0
T16	0	14372	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	370	0	0
T49	0	440	0	0
T51	0	414	0	0
T52	0	1151	0	0
T72	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	143712	0	0
T2	2535	512	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	365	0	0
T6	4843	0	0	0
T7	0	1071	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	219	0	0
T16	0	14632	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	371	0	0
T49	0	441	0	0
T51	0	415	0	0
T52	0	1152	0	0
T72	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T41,T42,T43
DataWait	75	Covered	T41,T42,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T2,T5,T7
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T176,T177,T186
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T41,T42,T43
DataWait->AckPls	80	Covered	T41,T42,T43
DataWait->Disabled	107	Covered	T66,T204
DataWait->Error	99	Covered	T31,T137
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T81,T187,T188
EndPointClear->Error	99	Covered	T16,T189,T190
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T41,T42,T43
Idle->Disabled	107	Covered	T2,T23,T4
Idle->Error	99	Covered	T2,T5,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T41,T42,T43
Idle	-	1	0	-	Covered	T41,T42,T43
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T41,T42,T43
DataWait	-	-	-	0	Covered	T41,T42,T43
AckPls	-	-	-	-	Covered	T41,T42,T43
Error	-	-	-	-	Covered	T2,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T23,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	201967009	142546	0	0
FpvSecCmErrorStEscalate_A	201967009	143712	0	0
u_state_regs_A	201967009	201788644	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	142546	0	0
T2	2535	511	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	364	0	0
T6	4843	0	0	0
T7	0	1070	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	218	0	0
T16	0	14372	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	370	0	0
T49	0	440	0	0
T51	0	414	0	0
T52	0	1151	0	0
T72	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	143712	0	0
T2	2535	512	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	365	0	0
T6	4843	0	0	0
T7	0	1071	0	0
T9	1635	0	0	0
T10	6771	0	0	0
T14	7605	0	0	0
T15	0	219	0	0
T16	0	14632	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T31	0	371	0	0
T49	0	441	0	0
T51	0	415	0	0
T52	0	1152	0	0
T72	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0