Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T36,T91
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T37,T38
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403208664	989353	0	0
DepthKnown_A	403934018	403577288	0	0
RvalidKnown_A	403934018	403577288	0	0
WreadyKnown_A	403934018	403577288	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	403556420	1079572	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403208664	989353	0	0
T2	886	466	0	0
T3	3478	0	0	0
T4	369218	0	0	0
T6	9686	0	0	0
T7	0	69	0	0
T9	3270	979	0	0
T10	13542	6664	0	0
T14	15210	11002	0	0
T19	0	2811	0	0
T20	0	2452	0	0
T22	4264	0	0	0
T23	2054	0	0	0
T24	4824	0	0	0
T28	0	624	0	0
T45	0	1938	0	0
T79	0	1328	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403934018	403577288	0	0
T1	5224	5092	0	0
T2	5070	4752	0	0
T3	3478	3336	0	0
T4	369218	369194	0	0
T6	9686	9518	0	0
T9	3270	3150	0	0
T10	13542	13366	0	0
T22	4264	4078	0	0
T23	2054	1878	0	0
T24	4824	4684	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403934018	403577288	0	0
T1	5224	5092	0	0
T2	5070	4752	0	0
T3	3478	3336	0	0
T4	369218	369194	0	0
T6	9686	9518	0	0
T9	3270	3150	0	0
T10	13542	13366	0	0
T22	4264	4078	0	0
T23	2054	1878	0	0
T24	4824	4684	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403934018	403577288	0	0
T1	5224	5092	0	0
T2	5070	4752	0	0
T3	3478	3336	0	0
T4	369218	369194	0	0
T6	9686	9518	0	0
T9	3270	3150	0	0
T10	13542	13366	0	0
T22	4264	4078	0	0
T23	2054	1878	0	0
T24	4824	4684	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	403556420	1079572	0	0
T2	5070	3374	0	0
T3	3478	0	0	0
T4	369218	0	0	0
T5	0	2261	0	0
T6	9686	0	0	0
T7	0	1526	0	0
T9	3270	979	0	0
T10	13542	6664	0	0
T14	15210	11002	0	0
T15	0	282	0	0
T19	0	2811	0	0
T20	0	2452	0	0
T22	4264	0	0	0
T23	2054	0	0	0
T24	4824	0	0	0
T28	0	624	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T79,T33,T92
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T91,T93
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T94,T95
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	201604332	490035	0	0
DepthKnown_A	201967009	201788644	0	0
RvalidKnown_A	201967009	201788644	0	0
WreadyKnown_A	201967009	201788644	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	201778210	534780	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201604332	490035	0	0
T2	443	200	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T6	4843	0	0	0
T7	0	27	0	0
T9	1635	478	0	0
T10	6771	3302	0	0
T14	7605	5477	0	0
T19	0	1368	0	0
T20	0	1212	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T28	0	315	0	0
T45	0	921	0	0
T79	0	669	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	201778210	534780	0	0
T2	2535	1587	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	1135	0	0
T6	4843	0	0	0
T7	0	747	0	0
T9	1635	478	0	0
T10	6771	3302	0	0
T14	7605	5477	0	0
T15	0	145	0	0
T19	0	1368	0	0
T20	0	1212	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T28	0	315	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36,T96
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T37,T38
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	201604332	499318	0	0
DepthKnown_A	201967009	201788644	0	0
RvalidKnown_A	201967009	201788644	0	0
WreadyKnown_A	201967009	201788644	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	201778210	544792	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201604332	499318	0	0
T2	443	266	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T6	4843	0	0	0
T7	0	42	0	0
T9	1635	501	0	0
T10	6771	3362	0	0
T14	7605	5525	0	0
T19	0	1443	0	0
T20	0	1240	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T28	0	309	0	0
T45	0	1017	0	0
T79	0	659	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201967009	201788644	0	0
T1	2612	2546	0	0
T2	2535	2376	0	0
T3	1739	1668	0	0
T4	184609	184597	0	0
T6	4843	4759	0	0
T9	1635	1575	0	0
T10	6771	6683	0	0
T22	2132	2039	0	0
T23	1027	939	0	0
T24	2412	2342	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	201778210	544792	0	0
T2	2535	1787	0	0
T3	1739	0	0	0
T4	184609	0	0	0
T5	0	1126	0	0
T6	4843	0	0	0
T7	0	779	0	0
T9	1635	501	0	0
T10	6771	3362	0	0
T14	7605	5525	0	0
T15	0	137	0	0
T19	0	1443	0	0
T20	0	1240	0	0
T22	2132	0	0	0
T23	1027	0	0	0
T24	2412	0	0	0
T28	0	309	0	0