Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	623535	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4769645

1

T1

26

T2

68

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1447174	1			T1	48		T2	43		T3	1
values[0x0]	1826717	1			T1	16		T2	32		T3	11
values[0x1]	2119289	1			T1	12		T2	37		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	315143	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5078037

1

T1

38

T2

84

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20297	1			T19	4		T22	4		T6	466
valid_sources[0x01]	21262	1			T3	1		T20	1		T5	3
valid_sources[0x02]	20865	1			T20	3		T5	1		T25	34
valid_sources[0x03]	21585	1			T19	3		T75	1		T6	348
valid_sources[0x04]	23341	1			T19	3		T23	1		T6	408
valid_sources[0x05]	20388	1			T19	2		T20	1		T49	2
valid_sources[0x06]	21029	1			T1	1		T20	3		T23	2
valid_sources[0x07]	19117	1			T20	2		T75	2		T6	269
valid_sources[0x08]	21191	1			T20	1		T4	1		T5	2
valid_sources[0x09]	21265	1			T20	3		T45	2		T6	385
valid_sources[0x0a]	20813	1			T20	3		T6	404		T38	236
valid_sources[0x0b]	19782	1			T6	516		T38	268		T106	2
valid_sources[0x0c]	21444	1			T20	1		T49	1		T6	378
valid_sources[0x0d]	19388	1			T1	2		T3	1		T75	1
valid_sources[0x0e]	21340	1			T20	5		T21	8		T23	7
valid_sources[0x0f]	20205	1			T19	1		T20	1		T6	348
valid_sources[0x10]	20838	1			T20	2		T6	321		T38	265
valid_sources[0x11]	20784	1			T19	2		T20	1		T6	502
valid_sources[0x12]	18972	1			T6	402		T38	285		T39	897
valid_sources[0x13]	21357	1			T19	6		T6	306		T38	270
valid_sources[0x14]	21089	1			T29	27		T6	349		T38	277
valid_sources[0x15]	20007	1			T3	3		T20	1		T4	1
valid_sources[0x16]	21932	1			T3	1		T4	1		T58	14
valid_sources[0x17]	19073	1			T20	5		T75	1		T6	355
valid_sources[0x18]	19381	1			T20	2		T76	2		T6	412
valid_sources[0x19]	22314	1			T23	1		T28	7		T5	1
valid_sources[0x1a]	22210	1			T1	1		T75	1		T6	377
valid_sources[0x1b]	20492	1			T75	2		T6	454		T38	246
valid_sources[0x1c]	21098	1			T4	1		T6	366		T38	271
valid_sources[0x1d]	19952	1			T1	1		T19	1		T75	1
valid_sources[0x1e]	20905	1			T20	4		T4	1		T6	300
valid_sources[0x1f]	19765	1			T20	1		T4	1		T49	1
valid_sources[0x20]	21718	1			T23	1		T49	21		T58	23
valid_sources[0x21]	20265	1			T6	399		T38	211		T106	1
valid_sources[0x22]	20799	1			T20	1		T28	1		T6	367
valid_sources[0x23]	21867	1			T20	2		T75	1		T5	2
valid_sources[0x24]	22455	1			T75	1		T6	326		T38	256
valid_sources[0x25]	20728	1			T28	2		T76	1		T6	401
valid_sources[0x26]	20961	1			T20	2		T76	1		T6	465
valid_sources[0x27]	22094	1			T20	4		T76	1		T6	477
valid_sources[0x28]	20533	1			T49	1		T6	360		T38	239
valid_sources[0x29]	20861	1			T6	407		T38	298		T39	843
valid_sources[0x2a]	21398	1			T20	1		T6	425		T38	236
valid_sources[0x2b]	20999	1			T75	1		T4	1		T5	1
valid_sources[0x2c]	20001	1			T20	2		T23	1		T75	2
valid_sources[0x2d]	21409	1			T19	5		T75	1		T6	352
valid_sources[0x2e]	19534	1			T20	1		T58	6		T6	357
valid_sources[0x2f]	20229	1			T1	2		T75	1		T4	3
valid_sources[0x30]	21440	1			T23	1		T75	1		T4	1
valid_sources[0x31]	20595	1			T19	3		T20	3		T4	1
valid_sources[0x32]	21046	1			T6	407		T38	277		T39	834
valid_sources[0x33]	21518	1			T20	3		T4	3		T76	1
valid_sources[0x34]	20859	1			T3	1		T6	362		T38	299
valid_sources[0x35]	21341	1			T20	3		T28	1		T76	1
valid_sources[0x36]	21731	1			T20	2		T28	1		T6	431
valid_sources[0x37]	21848	1			T4	1		T6	384		T38	245
valid_sources[0x38]	19333	1			T20	2		T6	311		T38	219
valid_sources[0x39]	21792	1			T19	1		T20	1		T23	4
valid_sources[0x3a]	19671	1			T20	2		T6	382		T38	247
valid_sources[0x3b]	21339	1			T20	1		T23	3		T6	511
valid_sources[0x3c]	21559	1			T75	1		T6	387		T38	276
valid_sources[0x3d]	19735	1			T19	3		T20	3		T6	316
valid_sources[0x3e]	20995	1			T20	1		T75	1		T4	1
valid_sources[0x3f]	22362	1			T1	8		T6	430		T38	222
valid_sources[0x40]	21086	1			T1	1		T23	2		T58	3
valid_sources[0x41]	21109	1			T4	1		T6	419		T38	275
valid_sources[0x42]	22027	1			T6	341		T38	241		T39	891
valid_sources[0x43]	21773	1			T20	5		T6	387		T38	284
valid_sources[0x44]	20200	1			T76	3		T5	2		T49	2
valid_sources[0x45]	19488	1			T4	2		T49	1		T6	380
valid_sources[0x46]	21477	1			T23	2		T29	13		T58	12
valid_sources[0x47]	19659	1			T1	1		T4	2		T6	409
valid_sources[0x48]	20278	1			T19	3		T23	4		T6	363
valid_sources[0x49]	21096	1			T19	2		T29	6		T6	438
valid_sources[0x4a]	22401	1			T20	1		T6	429		T38	293
valid_sources[0x4b]	21261	1			T20	1		T49	2		T6	345
valid_sources[0x4c]	20747	1			T75	1		T4	1		T6	514
valid_sources[0x4d]	20910	1			T20	1		T4	1		T6	446
valid_sources[0x4e]	21197	1			T20	6		T6	413		T38	261
valid_sources[0x4f]	19359	1			T20	2		T5	2		T6	351
valid_sources[0x50]	21452	1			T19	6		T6	376		T38	265
valid_sources[0x51]	21482	1			T20	3		T6	396		T38	249
valid_sources[0x52]	20497	1			T1	1		T75	1		T29	5
valid_sources[0x53]	21704	1			T20	2		T6	389		T38	271
valid_sources[0x54]	21400	1			T23	2		T75	2		T76	1
valid_sources[0x55]	21566	1			T4	1		T6	470		T38	251
valid_sources[0x56]	21685	1			T4	1		T6	432		T38	247
valid_sources[0x57]	21718	1			T20	1		T75	1		T6	347
valid_sources[0x58]	20007	1			T4	1		T6	486		T38	270
valid_sources[0x59]	20686	1			T3	2		T19	1		T20	2
valid_sources[0x5a]	20112	1			T20	1		T4	2		T6	342
valid_sources[0x5b]	21986	1			T23	1		T58	3		T6	403
valid_sources[0x5c]	20328	1			T4	1		T6	292		T38	285
valid_sources[0x5d]	22168	1			T28	4		T58	2		T6	448
valid_sources[0x5e]	21664	1			T75	1		T6	408		T38	245
valid_sources[0x5f]	22869	1			T6	450		T38	259		T39	839
valid_sources[0x60]	22344	1			T19	3		T4	1		T76	3
valid_sources[0x61]	19944	1			T6	426		T38	230		T39	866
valid_sources[0x62]	21213	1			T4	2		T76	1		T6	298
valid_sources[0x63]	21719	1			T6	317		T38	259		T106	1
valid_sources[0x64]	19820	1			T20	1		T76	1		T6	441
valid_sources[0x65]	22282	1			T6	436		T38	293		T106	1
valid_sources[0x66]	21010	1			T1	1		T75	1		T6	435
valid_sources[0x67]	21114	1			T20	2		T75	1		T4	1
valid_sources[0x68]	20420	1			T20	3		T6	371		T38	253
valid_sources[0x69]	21932	1			T23	3		T75	1		T28	1
valid_sources[0x6a]	21390	1			T1	1		T3	1		T20	2
valid_sources[0x6b]	22673	1			T19	1		T6	346		T38	230
valid_sources[0x6c]	20750	1			T20	1		T75	1		T28	1
valid_sources[0x6d]	19856	1			T20	2		T6	389		T38	296
valid_sources[0x6e]	20530	1			T3	1		T20	5		T75	1
valid_sources[0x6f]	21770	1			T1	1		T19	3		T75	2
valid_sources[0x70]	19660	1			T1	1		T4	3		T76	1
valid_sources[0x71]	21228	1			T1	1		T19	1		T76	1
valid_sources[0x72]	19981	1			T1	1		T20	1		T6	406
valid_sources[0x73]	20473	1			T1	8		T20	2		T28	2
valid_sources[0x74]	20322	1			T28	3		T6	386		T38	245
valid_sources[0x75]	20646	1			T20	3		T75	1		T6	383
valid_sources[0x76]	21898	1			T20	3		T23	1		T4	1
valid_sources[0x77]	20804	1			T6	385		T38	229		T39	833
valid_sources[0x78]	20248	1			T3	2		T20	1		T75	2
valid_sources[0x79]	20208	1			T19	10		T20	1		T75	1
valid_sources[0x7a]	20342	1			T75	1		T6	423		T38	242
valid_sources[0x7b]	21649	1			T6	366		T38	246		T106	1
valid_sources[0x7c]	21573	1			T4	1		T5	1		T6	437
valid_sources[0x7d]	21939	1			T20	2		T6	377		T38	278
valid_sources[0x7e]	20530	1			T19	2		T58	3		T6	440
valid_sources[0x7f]	19992	1			T20	1		T75	1		T5	1
valid_sources[0x80]	21258	1			T75	1		T5	1		T6	402

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1203782

1

T1

11

T2

5

T7

1

values[0x0]

all_enables

biggest_size

1786462

1

T1

10

T2

29

T3

4

values[0x1]

all_enables

biggest_size

1779401

1

T1

5

T2

34

T3

2