Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2731	1			T2	2		T7	1		T20	1
non_zero_bins[1]	1994	1			T2	5		T7	2		T20	1
zero	9627	1			T1	8		T2	1		T7	19

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	529	1			T24	1		T58	1		T6	9
uni	3815	1			T1	1		T2	1		T7	1
gen	4579	1			T1	4		T2	4		T7	18
res	888	1			T2	2		T7	2		T20	1
ins	4541	1			T1	3		T2	1		T7	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9535

1

T1

4

T2

7

T7

22

mubi_true

4817

1

T1

4

T2

1

T20

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

24

1

T86

1

T162

1

T246

1

pass

14328

1

T1

8

T2

8

T7

22

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	131	1			T39	1		T79	1		T71	2
upd	non_zero_bins[0]	pass	mubi_true	125	1			T58	1		T6	2		T38	1
upd	non_zero_bins[1]	pass	mubi_false	81	1			T6	3		T38	1		T39	1
upd	non_zero_bins[1]	pass	mubi_true	94	1			T24	1		T6	2		T38	1
upd	zero	pass	mubi_false	47	1			T38	1		T71	1		T73	1
upd	zero	pass	mubi_true	51	1			T6	2		T38	1		T39	1
uni	zero	pass	mubi_false	2798	1			T1	1		T2	1		T7	1
uni	zero	pass	mubi_true	1017	1			T23	1		T75	1		T25	1
gen	non_zero_bins[0]	pass	mubi_false	523	1			T75	1		T16	3		T58	1
gen	non_zero_bins[0]	pass	mubi_true	464	1			T24	1		T40	1		T6	6
gen	non_zero_bins[1]	pass	mubi_false	399	1			T2	3		T6	1		T38	2
gen	non_zero_bins[1]	pass	mubi_true	376	1			T2	1		T22	1		T23	1
gen	zero	fail	mubi_false	21	1			T86	1		T246	1		T63	1
gen	zero	pass	mubi_false	2044	1			T1	2		T7	18		T19	2
gen	zero	pass	mubi_true	752	1			T1	2		T20	1		T24	1
res	non_zero_bins[0]	pass	mubi_false	205	1			T2	2		T22	1		T16	2
res	non_zero_bins[0]	pass	mubi_true	199	1			T20	1		T6	4		T101	2
res	non_zero_bins[1]	pass	mubi_false	150	1			T7	2		T6	1		T38	1
res	non_zero_bins[1]	pass	mubi_true	136	1			T39	2		T43	1		T71	1
res	zero	fail	mubi_false	3	1			T162	1		T292	1		T293	1
res	zero	pass	mubi_false	106	1			T38	1		T230	1		T42	2
res	zero	pass	mubi_true	89	1			T38	1		T39	1		T71	1
ins	non_zero_bins[0]	pass	mubi_false	527	1			T7	1		T24	1		T75	1
ins	non_zero_bins[0]	pass	mubi_true	557	1			T23	1		T58	1		T6	11
ins	non_zero_bins[1]	pass	mubi_false	390	1			T2	1		T20	1		T6	6
ins	non_zero_bins[1]	pass	mubi_true	368	1			T23	1		T75	1		T40	2
ins	zero	pass	mubi_false	2110	1			T1	1		T19	2		T20	1
ins	zero	pass	mubi_true	589	1			T1	2		T22	1		T24	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded