Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T45,T94,T84
1	1	Covered	T1,T20,T24

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T4,T5,T8
1	1	Covered	T1,T2,T7

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T28,T29
1	0	Covered	T4,T5,T8

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T28,T29
1	Covered	T4,T5,T8

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T28,T29
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T28,T4
1	Covered	T4,T5,T8

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T28,T4

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T2,T7
AutoCaptGenCnt	143	Covered	T1,T2,T7
AutoCaptReseedCnt	141	Covered	T1,T2,T7
AutoDispatch	125	Covered	T1,T2,T7
AutoFirstAckWait	119	Covered	T1,T2,T7
AutoLoadIns	69	Covered	T1,T2,T7
AutoSendGenCmd	150	Covered	T1,T2,T7
AutoSendReseedCmd	162	Covered	T2,T7,T16
BootDone	98	Covered	T1,T20,T24
BootGenAckWait	90	Covered	T1,T20,T24
BootInsAckWait	80	Covered	T1,T20,T24
BootLoadGen	85	Covered	T1,T20,T24
BootLoadIns	65	Covered	T1,T20,T24
BootLoadUni	102	Covered	T1,T20,T24
BootPulse	94	Covered	T1,T20,T24
BootUniAckWait	107	Covered	T1,T20,T24
Error	188	Covered	T4,T5,T8
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T28,T29
SWPortMode	74	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T2,T7
AutoAckWait->Error	188	Covered	T118,T119,T120
AutoAckWait->Idle	211	Covered	T97,T121,T122
AutoAckWait->RejectCsrngEntropy	188	Covered	T117,T95,T86
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T2,T7
AutoCaptGenCnt->Error	188	Covered	T123,T124,T125
AutoCaptGenCnt->Idle	211	Covered	T126,T127,T128
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T129,T130,T131
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T7,T16
AutoCaptReseedCnt->Error	188	Covered	T5,T78,T132
AutoCaptReseedCnt->Idle	211	Covered	T121,T133,T134
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T1,T29,T135
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T2,T7
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T2,T7
AutoDispatch->Error	188	Covered	T136,T137,T138
AutoDispatch->Idle	138	Covered	T2,T7,T16
AutoDispatch->RejectCsrngEntropy	188	Covered	T139,T140,T141
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T2,T7
AutoFirstAckWait->Error	188	Covered	T142,T143,T144
AutoFirstAckWait->Idle	211	Covered	T145,T146,T147
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T50,T87,T110
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T2,T7
AutoLoadIns->Error	188	Covered	T8,T54,T56
AutoLoadIns->Idle	211	Covered	T4,T5,T49
AutoLoadIns->RejectCsrngEntropy	188	Covered	T148,T149,T150
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T2,T7
AutoSendGenCmd->Error	188	Covered	T111,T151,T152
AutoSendGenCmd->Idle	211	Covered	T153,T154,T155
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T156,T157,T112
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T7,T16
AutoSendReseedCmd->Error	188	Covered	T158,T159
AutoSendReseedCmd->Idle	211	Covered	T97,T160,T161
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T162,T163,T164
BootDone->BootLoadUni	102	Covered	T1,T20,T24
BootDone->Error	188	Covered	T165
BootDone->Idle	211	Covered	T166,T167,T168
BootDone->RejectCsrngEntropy	188	Covered	T169,T88,T170
BootGenAckWait->BootPulse	94	Covered	T1,T20,T24
BootGenAckWait->Error	188	Not Covered
BootGenAckWait->Idle	211	Covered	T45,T51,T77
BootGenAckWait->RejectCsrngEntropy	188	Covered	T171,T172,T173
BootInsAckWait->BootLoadGen	85	Covered	T1,T20,T24
BootInsAckWait->Error	188	Covered	T51,T174,T175
BootInsAckWait->Idle	211	Covered	T52,T91,T105
BootInsAckWait->RejectCsrngEntropy	188	Covered	T176,T177,T178
BootLoadGen->BootGenAckWait	90	Covered	T1,T20,T24
BootLoadGen->Error	188	Covered	T179,T180
BootLoadGen->Idle	211	Covered	T96,T181,T182
BootLoadGen->RejectCsrngEntropy	188	Covered	T183,T184
BootLoadIns->BootInsAckWait	80	Covered	T1,T20,T24
BootLoadIns->Error	188	Covered	T52,T182,T185
BootLoadIns->Idle	211	Covered	T84,T186,T187
BootLoadIns->RejectCsrngEntropy	188	Covered	T28,T49,T80
BootLoadUni->BootUniAckWait	107	Covered	T1,T20,T24
BootLoadUni->Error	188	Covered	T188
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T189,T190,T191
BootPulse->BootDone	98	Covered	T1,T20,T24
BootPulse->Error	188	Covered	T192,T193
BootPulse->Idle	211	Covered	T94,T82,T194
BootPulse->RejectCsrngEntropy	188	Covered	T195,T196,T197
BootUniAckWait->Error	188	Covered	T198
BootUniAckWait->Idle	112	Covered	T1,T20,T24
BootUniAckWait->RejectCsrngEntropy	188	Covered	T76,T81,T199
Idle->AutoLoadIns	69	Covered	T1,T2,T7
Idle->BootLoadIns	65	Covered	T1,T20,T24
Idle->Error	188	Covered	T13,T14,T15
Idle->RejectCsrngEntropy	188	Covered	T1,T29,T76
Idle->SWPortMode	74	Covered	T1,T2,T7
RejectCsrngEntropy->Error	188	Covered	T103,T200,T201
RejectCsrngEntropy->Idle	211	Covered	T1,T28,T29
SWPortMode->Error	188	Covered	T12,T53,T55
SWPortMode->Idle	211	Covered	T28,T29,T6
SWPortMode->RejectCsrngEntropy	188	Covered	T28,T49,T81

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T76,T45
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T24
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T20,T24,T76
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T20,T24
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T7
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T7
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T7
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T7
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T7
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T7
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T7,T16
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T7
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T2,T7
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T7
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T7,T5
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T7,T16
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T16
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T28,T29
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T77,T105

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T5,T8
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T28,T29
0	-	-	1	Covered	T1,T28,T4
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	189697645	174541	0	0
FpvSecCmErrorStEscalate_A	189697645	175975	0	0
u_state_regs_A	189654523	189442235	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	174541	0	0
T4	2027	1020	0	0
T5	2545	1147	0	0
T8	0	592	0	0
T12	0	1068	0	0
T16	8336	0	0	0
T25	885	0	0	0
T29	2306	0	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	431	0	0
T52	0	378	0	0
T53	0	1172	0	0
T54	0	630	0	0
T58	2802	0	0	0
T76	2066	0	0	0
T77	0	1064	0	0
T78	0	665	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	175975	0	0
T4	2027	1021	0	0
T5	2545	1148	0	0
T8	0	593	0	0
T12	0	1069	0	0
T16	8336	0	0	0
T25	885	0	0	0
T29	2306	0	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	432	0	0
T52	0	379	0	0
T53	0	1173	0	0
T54	0	631	0	0
T58	2802	0	0	0
T76	2066	0	0	0
T77	0	1065	0	0
T78	0	666	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189654523	189442235	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0