Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Module : edn_ack_sm
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T28,T4

FSM Coverage for Module : edn_ack_sm
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T1,T2,T7
DataWait 75 Covered T1,T2,T7
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T7
Error 99 Covered T4,T5,T8
Idle 68 Covered T1,T2,T7


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T94,T82,T194
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T2,T7
DataWait->AckPls 80 Covered T1,T2,T7
DataWait->Disabled 107 Covered T91,T153,T127
DataWait->Error 99 Covered T4,T8,T51
Disabled->EndPointClear 63 Covered T1,T2,T7
Disabled->Error 99 Covered T13,T14,T15
EndPointClear->Disabled 107 Covered T106,T73,T84
EndPointClear->Error 99 Covered T52,T104,T13
EndPointClear->Idle 68 Covered T1,T2,T7
Idle->DataWait 75 Covered T1,T2,T7
Idle->Disabled 107 Covered T1,T28,T4
Idle->Error 99 Covered T4,T5,T8



Branch Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T7
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T7
Idle - 1 1 - Covered T1,T2,T7
Idle - 1 0 - Covered T1,T2,T7
Idle - 0 - - Covered T1,T2,T7
DataWait - - - 1 Covered T1,T2,T7
DataWait - - - 0 Covered T2,T7,T19
AckPls - - - - Covered T1,T2,T7
Error - - - - Covered T4,T5,T8
default - - - - Covered T78,T103,T104


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T8
0 1 Covered T1,T28,T4
0 0 Covered T1,T2,T3


Assert Coverage for Module : edn_ack_sm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 1327883515 1237087 0 0
FpvSecCmErrorStEscalate_A 1327883515 1247125 0 0
u_state_regs_A 1327840393 1326354377 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1327883515 1237087 0 0
T4 14189 7490 0 0
T5 17815 8029 0 0
T8 0 4144 0 0
T12 0 7476 0 0
T16 58352 0 0 0
T25 6195 0 0 0
T29 16142 0 0 0
T40 21693 0 0 0
T45 8001 0 0 0
T49 10682 0 0 0
T51 0 3017 0 0
T52 0 2646 0 0
T53 0 8204 0 0
T54 0 4410 0 0
T58 19614 0 0 0
T76 14462 0 0 0
T77 0 7798 0 0
T78 0 4605 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1327883515 1247125 0 0
T4 14189 7497 0 0
T5 17815 8036 0 0
T8 0 4151 0 0
T12 0 7483 0 0
T16 58352 0 0 0
T25 6195 0 0 0
T29 16142 0 0 0
T40 21693 0 0 0
T45 8001 0 0 0
T49 10682 0 0 0
T51 0 3024 0 0
T52 0 2653 0 0
T53 0 8211 0 0
T54 0 4417 0 0
T58 19614 0 0 0
T76 14462 0 0 0
T77 0 7805 0 0
T78 0 4612 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1327840393 1326354377 0 0
T1 19054 18494 0 0
T2 13867 13321 0 0
T3 8260 7735 0 0
T7 20013 19502 0 0
T19 22393 21721 0 0
T20 28889 28350 0 0
T21 5299 4809 0 0
T22 9429 8890 0 0
T23 16884 16513 0 0
T24 14133 13580 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T28,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T2,T7,T19
DataWait 75 Covered T2,T7,T19
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T7
Error 99 Covered T4,T5,T8
Idle 68 Covered T1,T2,T7


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T2,T7,T19
DataWait->AckPls 80 Covered T2,T7,T19
DataWait->Disabled 107 Covered T202,T203,T204
DataWait->Error 99 Covered T8,T51,T56
Disabled->EndPointClear 63 Covered T1,T2,T7
Disabled->Error 99 Covered T13,T14,T15
EndPointClear->Disabled 107 Covered T106,T73,T84
EndPointClear->Error 99 Covered T52,T13,T14
EndPointClear->Idle 68 Covered T1,T2,T7
Idle->DataWait 75 Covered T2,T7,T19
Idle->Disabled 107 Covered T1,T28,T4
Idle->Error 99 Covered T4,T5,T12



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T7
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T7
Idle - 1 1 - Covered T2,T7,T19
Idle - 1 0 - Covered T2,T7,T19
Idle - 0 - - Covered T1,T2,T7
DataWait - - - 1 Covered T2,T7,T19
DataWait - - - 0 Covered T2,T7,T19
AckPls - - - - Covered T2,T7,T19
Error - - - - Covered T4,T5,T8
default - - - - Covered T78,T103,T104


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T8
0 1 Covered T1,T28,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 189697645 175141 0 0
FpvSecCmErrorStEscalate_A 189697645 176575 0 0
u_state_regs_A 189654523 189442235 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 175141 0 0
T4 2027 1070 0 0
T5 2545 1147 0 0
T8 0 592 0 0
T12 0 1068 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 431 0 0
T52 0 378 0 0
T53 0 1172 0 0
T54 0 630 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1114 0 0
T78 0 615 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 176575 0 0
T4 2027 1071 0 0
T5 2545 1148 0 0
T8 0 593 0 0
T12 0 1069 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 432 0 0
T52 0 379 0 0
T53 0 1173 0 0
T54 0 631 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1115 0 0
T78 0 616 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189654523 189442235 0 0
T1 2722 2642 0 0
T2 1981 1903 0 0
T3 1180 1105 0 0
T7 2859 2786 0 0
T19 3199 3103 0 0
T20 4127 4050 0 0
T21 757 687 0 0
T22 1347 1270 0 0
T23 2412 2359 0 0
T24 2019 1940 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T28,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T20,T40,T16
DataWait 75 Covered T20,T40,T16
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T7
Error 99 Covered T4,T5,T8
Idle 68 Covered T1,T2,T7


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T20,T40,T16
DataWait->AckPls 80 Covered T20,T40,T16
DataWait->Disabled 107 Covered T205,T206,T207
DataWait->Error 99 Covered T208,T209,T210
Disabled->EndPointClear 63 Covered T1,T2,T7
Disabled->Error 99 Covered T13,T14,T15
EndPointClear->Disabled 107 Covered T106,T73,T84
EndPointClear->Error 99 Covered T52,T104,T13
EndPointClear->Idle 68 Covered T1,T2,T7
Idle->DataWait 75 Covered T20,T40,T16
Idle->Disabled 107 Covered T1,T28,T4
Idle->Error 99 Covered T4,T5,T8



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T7
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T7
Idle - 1 1 - Covered T20,T40,T16
Idle - 1 0 - Covered T20,T40,T16
Idle - 0 - - Covered T1,T2,T7
DataWait - - - 1 Covered T20,T40,T16
DataWait - - - 0 Covered T20,T40,T16
AckPls - - - - Covered T20,T40,T16
Error - - - - Covered T4,T5,T8
default - - - - Covered T13,T14,T15


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T8
0 1 Covered T1,T28,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 189697645 176991 0 0
FpvSecCmErrorStEscalate_A 189697645 178425 0 0
u_state_regs_A 189697645 189485357 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 176991 0 0
T4 2027 1070 0 0
T5 2545 1147 0 0
T8 0 592 0 0
T12 0 1068 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 431 0 0
T52 0 378 0 0
T53 0 1172 0 0
T54 0 630 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1114 0 0
T78 0 665 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 178425 0 0
T4 2027 1071 0 0
T5 2545 1148 0 0
T8 0 593 0 0
T12 0 1069 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 432 0 0
T52 0 379 0 0
T53 0 1173 0 0
T54 0 631 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1115 0 0
T78 0 666 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 189485357 0 0
T1 2722 2642 0 0
T2 1981 1903 0 0
T3 1180 1105 0 0
T7 2859 2786 0 0
T19 3199 3103 0 0
T20 4127 4050 0 0
T21 757 687 0 0
T22 1347 1270 0 0
T23 2412 2359 0 0
T24 2019 1940 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T28,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T1,T7,T20
DataWait 75 Covered T1,T7,T20
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T7
Error 99 Covered T4,T5,T8
Idle 68 Covered T1,T2,T7


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T7,T20
DataWait->AckPls 80 Covered T1,T7,T20
DataWait->Disabled 107 Covered T211
DataWait->Error 99 Covered T77,T54,T212
Disabled->EndPointClear 63 Covered T1,T2,T7
Disabled->Error 99 Covered T13,T14,T15
EndPointClear->Disabled 107 Covered T106,T73,T84
EndPointClear->Error 99 Covered T52,T104,T13
EndPointClear->Idle 68 Covered T1,T2,T7
Idle->DataWait 75 Covered T1,T7,T20
Idle->Disabled 107 Covered T1,T28,T4
Idle->Error 99 Covered T4,T5,T8



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T7
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T7
Idle - 1 1 - Covered T1,T7,T20
Idle - 1 0 - Covered T1,T7,T20
Idle - 0 - - Covered T1,T2,T7
DataWait - - - 1 Covered T1,T7,T20
DataWait - - - 0 Covered T1,T7,T20
AckPls - - - - Covered T1,T7,T20
Error - - - - Covered T4,T5,T8
default - - - - Covered T13,T14,T15


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T8
0 1 Covered T1,T28,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 189697645 176991 0 0
FpvSecCmErrorStEscalate_A 189697645 178425 0 0
u_state_regs_A 189697645 189485357 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 176991 0 0
T4 2027 1070 0 0
T5 2545 1147 0 0
T8 0 592 0 0
T12 0 1068 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 431 0 0
T52 0 378 0 0
T53 0 1172 0 0
T54 0 630 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1114 0 0
T78 0 665 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 178425 0 0
T4 2027 1071 0 0
T5 2545 1148 0 0
T8 0 593 0 0
T12 0 1069 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 432 0 0
T52 0 379 0 0
T53 0 1173 0 0
T54 0 631 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1115 0 0
T78 0 666 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 189485357 0 0
T1 2722 2642 0 0
T2 1981 1903 0 0
T3 1180 1105 0 0
T7 2859 2786 0 0
T19 3199 3103 0 0
T20 4127 4050 0 0
T21 757 687 0 0
T22 1347 1270 0 0
T23 2412 2359 0 0
T24 2019 1940 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T28,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T7,T23,T40
DataWait 75 Covered T7,T23,T40
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T7
Error 99 Covered T4,T5,T8
Idle 68 Covered T1,T2,T7


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T194
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T7,T23,T40
DataWait->AckPls 80 Covered T7,T23,T40
DataWait->Disabled 107 Covered T153,T127,T213
DataWait->Error 99 Covered T105,T214,T103
Disabled->EndPointClear 63 Covered T1,T2,T7
Disabled->Error 99 Covered T13,T14,T15
EndPointClear->Disabled 107 Covered T106,T73,T84
EndPointClear->Error 99 Covered T52,T104,T13
EndPointClear->Idle 68 Covered T1,T2,T7
Idle->DataWait 75 Covered T7,T23,T40
Idle->Disabled 107 Covered T1,T28,T4
Idle->Error 99 Covered T4,T5,T8



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T7
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T7
Idle - 1 1 - Covered T7,T23,T40
Idle - 1 0 - Covered T7,T23,T40
Idle - 0 - - Covered T1,T2,T7
DataWait - - - 1 Covered T7,T23,T40
DataWait - - - 0 Covered T7,T23,T40
AckPls - - - - Covered T7,T23,T40
Error - - - - Covered T4,T5,T8
default - - - - Covered T13,T14,T15


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T8
0 1 Covered T1,T28,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 189697645 176991 0 0
FpvSecCmErrorStEscalate_A 189697645 178425 0 0
u_state_regs_A 189697645 189485357 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 176991 0 0
T4 2027 1070 0 0
T5 2545 1147 0 0
T8 0 592 0 0
T12 0 1068 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 431 0 0
T52 0 378 0 0
T53 0 1172 0 0
T54 0 630 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1114 0 0
T78 0 665 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 178425 0 0
T4 2027 1071 0 0
T5 2545 1148 0 0
T8 0 593 0 0
T12 0 1069 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 432 0 0
T52 0 379 0 0
T53 0 1173 0 0
T54 0 631 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1115 0 0
T78 0 666 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 189485357 0 0
T1 2722 2642 0 0
T2 1981 1903 0 0
T3 1180 1105 0 0
T7 2859 2786 0 0
T19 3199 3103 0 0
T20 4127 4050 0 0
T21 757 687 0 0
T22 1347 1270 0 0
T23 2412 2359 0 0
T24 2019 1940 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T28,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T1,T7,T20
DataWait 75 Covered T1,T7,T20
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T7
Error 99 Covered T4,T5,T8
Idle 68 Covered T1,T2,T7


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T82
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T7,T20
DataWait->AckPls 80 Covered T1,T7,T20
DataWait->Disabled 107 Covered T215,T216
DataWait->Error 99 Covered T4,T192,T143
Disabled->EndPointClear 63 Covered T1,T2,T7
Disabled->Error 99 Covered T13,T14,T15
EndPointClear->Disabled 107 Covered T106,T73,T84
EndPointClear->Error 99 Covered T52,T104,T13
EndPointClear->Idle 68 Covered T1,T2,T7
Idle->DataWait 75 Covered T1,T7,T20
Idle->Disabled 107 Covered T1,T28,T4
Idle->Error 99 Covered T5,T8,T12



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T7
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T7
Idle - 1 1 - Covered T1,T7,T20
Idle - 1 0 - Covered T1,T7,T20
Idle - 0 - - Covered T1,T2,T7
DataWait - - - 1 Covered T1,T7,T20
DataWait - - - 0 Covered T7,T20,T4
AckPls - - - - Covered T1,T7,T20
Error - - - - Covered T4,T5,T8
default - - - - Covered T13,T14,T15


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T8
0 1 Covered T1,T28,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 189697645 176991 0 0
FpvSecCmErrorStEscalate_A 189697645 178425 0 0
u_state_regs_A 189697645 189485357 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 176991 0 0
T4 2027 1070 0 0
T5 2545 1147 0 0
T8 0 592 0 0
T12 0 1068 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 431 0 0
T52 0 378 0 0
T53 0 1172 0 0
T54 0 630 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1114 0 0
T78 0 665 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 178425 0 0
T4 2027 1071 0 0
T5 2545 1148 0 0
T8 0 593 0 0
T12 0 1069 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 432 0 0
T52 0 379 0 0
T53 0 1173 0 0
T54 0 631 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1115 0 0
T78 0 666 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 189485357 0 0
T1 2722 2642 0 0
T2 1981 1903 0 0
T3 1180 1105 0 0
T7 2859 2786 0 0
T19 3199 3103 0 0
T20 4127 4050 0 0
T21 757 687 0 0
T22 1347 1270 0 0
T23 2412 2359 0 0
T24 2019 1940 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T28,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T7,T41,T17
DataWait 75 Covered T7,T41,T17
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T7
Error 99 Covered T4,T5,T8
Idle 68 Covered T1,T2,T7


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T217
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T7,T41,T17
DataWait->AckPls 80 Covered T7,T41,T17
DataWait->Disabled 107 Covered T91,T218,T219
DataWait->Error 99 Covered T165,T220,T119
Disabled->EndPointClear 63 Covered T1,T2,T7
Disabled->Error 99 Covered T13,T14,T15
EndPointClear->Disabled 107 Covered T106,T73,T84
EndPointClear->Error 99 Covered T52,T104,T13
EndPointClear->Idle 68 Covered T1,T2,T7
Idle->DataWait 75 Covered T7,T41,T17
Idle->Disabled 107 Covered T1,T28,T4
Idle->Error 99 Covered T4,T5,T8



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T7
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T7
Idle - 1 1 - Covered T7,T41,T17
Idle - 1 0 - Covered T7,T41,T17
Idle - 0 - - Covered T1,T2,T7
DataWait - - - 1 Covered T7,T41,T17
DataWait - - - 0 Covered T7,T41,T17
AckPls - - - - Covered T7,T41,T17
Error - - - - Covered T4,T5,T8
default - - - - Covered T13,T14,T15


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T8
0 1 Covered T1,T28,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 189697645 176991 0 0
FpvSecCmErrorStEscalate_A 189697645 178425 0 0
u_state_regs_A 189697645 189485357 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 176991 0 0
T4 2027 1070 0 0
T5 2545 1147 0 0
T8 0 592 0 0
T12 0 1068 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 431 0 0
T52 0 378 0 0
T53 0 1172 0 0
T54 0 630 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1114 0 0
T78 0 665 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 178425 0 0
T4 2027 1071 0 0
T5 2545 1148 0 0
T8 0 593 0 0
T12 0 1069 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 432 0 0
T52 0 379 0 0
T53 0 1173 0 0
T54 0 631 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1115 0 0
T78 0 666 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 189485357 0 0
T1 2722 2642 0 0
T2 1981 1903 0 0
T3 1180 1105 0 0
T7 2859 2786 0 0
T19 3199 3103 0 0
T20 4127 4050 0 0
T21 757 687 0 0
T22 1347 1270 0 0
T23 2412 2359 0 0
T24 2019 1940 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T28,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T7,T29,T16
DataWait 75 Covered T7,T29,T16
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T7
Error 99 Covered T4,T5,T8
Idle 68 Covered T1,T2,T7


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T94
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T7,T29,T16
DataWait->AckPls 80 Covered T7,T29,T16
DataWait->Disabled 107 Covered T96,T181,T221
DataWait->Error 99 Covered T222,T118,T198
Disabled->EndPointClear 63 Covered T1,T2,T7
Disabled->Error 99 Covered T13,T14,T15
EndPointClear->Disabled 107 Covered T106,T73,T84
EndPointClear->Error 99 Covered T52,T104,T13
EndPointClear->Idle 68 Covered T1,T2,T7
Idle->DataWait 75 Covered T7,T29,T16
Idle->Disabled 107 Covered T1,T28,T4
Idle->Error 99 Covered T4,T5,T8



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T7
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T7
Idle - 1 1 - Covered T7,T29,T16
Idle - 1 0 - Covered T7,T29,T16
Idle - 0 - - Covered T1,T2,T7
DataWait - - - 1 Covered T7,T29,T16
DataWait - - - 0 Covered T7,T29,T16
AckPls - - - - Covered T7,T29,T16
Error - - - - Covered T4,T5,T8
default - - - - Covered T13,T14,T15


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T8
0 1 Covered T1,T28,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 189697645 176991 0 0
FpvSecCmErrorStEscalate_A 189697645 178425 0 0
u_state_regs_A 189697645 189485357 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 176991 0 0
T4 2027 1070 0 0
T5 2545 1147 0 0
T8 0 592 0 0
T12 0 1068 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 431 0 0
T52 0 378 0 0
T53 0 1172 0 0
T54 0 630 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1114 0 0
T78 0 665 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 178425 0 0
T4 2027 1071 0 0
T5 2545 1148 0 0
T8 0 593 0 0
T12 0 1069 0 0
T16 8336 0 0 0
T25 885 0 0 0
T29 2306 0 0 0
T40 3099 0 0 0
T45 1143 0 0 0
T49 1526 0 0 0
T51 0 432 0 0
T52 0 379 0 0
T53 0 1173 0 0
T54 0 631 0 0
T58 2802 0 0 0
T76 2066 0 0 0
T77 0 1115 0 0
T78 0 666 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189697645 189485357 0 0
T1 2722 2642 0 0
T2 1981 1903 0 0
T3 1180 1105 0 0
T7 2859 2786 0 0
T19 3199 3103 0 0
T20 4127 4050 0 0
T21 757 687 0 0
T22 1347 1270 0 0
T23 2412 2359 0 0
T24 2019 1940 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%