Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T98,T99,T100
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T32,T37
1	0	1	Covered	T1,T2,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	378503460	1163737	0	0
DepthKnown_A	379395290	378970714	0	0
RvalidKnown_A	379395290	378970714	0	0
WreadyKnown_A	379395290	378970714	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	378885574	1268452	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378503460	1163737	0	0
T1	5444	657	0	0
T2	3962	1568	0	0
T3	2360	0	0	0
T4	0	69	0	0
T5	0	226	0	0
T7	5718	2620	0	0
T16	0	12914	0	0
T19	6398	0	0	0
T20	8254	0	0	0
T21	1514	0	0	0
T22	2694	0	0	0
T23	4824	0	0	0
T24	4038	0	0	0
T29	0	698	0	0
T49	0	97	0	0
T50	0	984	0	0
T101	0	3323	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379395290	378970714	0	0
T1	5444	5284	0	0
T2	3962	3806	0	0
T3	2360	2210	0	0
T7	5718	5572	0	0
T19	6398	6206	0	0
T20	8254	8100	0	0
T21	1514	1374	0	0
T22	2694	2540	0	0
T23	4824	4718	0	0
T24	4038	3880	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379395290	378970714	0	0
T1	5444	5284	0	0
T2	3962	3806	0	0
T3	2360	2210	0	0
T7	5718	5572	0	0
T19	6398	6206	0	0
T20	8254	8100	0	0
T21	1514	1374	0	0
T22	2694	2540	0	0
T23	4824	4718	0	0
T24	4038	3880	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379395290	378970714	0	0
T1	5444	5284	0	0
T2	3962	3806	0	0
T3	2360	2210	0	0
T7	5718	5572	0	0
T19	6398	6206	0	0
T20	8254	8100	0	0
T21	1514	1374	0	0
T22	2694	2540	0	0
T23	4824	4718	0	0
T24	4038	3880	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	378885574	1268452	0	0
T1	5444	657	0	0
T2	3962	1568	0	0
T3	2360	0	0	0
T4	0	1631	0	0
T5	0	2144	0	0
T7	5718	2620	0	0
T16	0	12914	0	0
T19	6398	0	0	0
T20	8254	0	0	0
T21	1514	0	0	0
T22	2694	0	0	0
T23	4824	0	0	0
T24	4038	0	0	0
T29	0	698	0	0
T49	0	97	0	0
T50	0	984	0	0
T101	0	3323	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T56
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T98,T99
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T37
1	0	1	Covered	T1,T2,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	189251730	575182	0	0
DepthKnown_A	189697645	189485357	0	0
RvalidKnown_A	189697645	189485357	0	0
WreadyKnown_A	189697645	189485357	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	189442787	627212	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189251730	575182	0	0
T1	2722	331	0	0
T2	1981	754	0	0
T3	1180	0	0	0
T4	0	33	0	0
T5	0	79	0	0
T7	2859	1315	0	0
T16	0	6416	0	0
T19	3199	0	0	0
T20	4127	0	0	0
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	0	0	0
T24	2019	0	0	0
T29	0	354	0	0
T49	0	41	0	0
T50	0	486	0	0
T101	0	1651	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	189442787	627212	0	0
T1	2722	331	0	0
T2	1981	754	0	0
T3	1180	0	0	0
T4	0	816	0	0
T5	0	992	0	0
T7	2859	1315	0	0
T16	0	6416	0	0
T19	3199	0	0	0
T20	4127	0	0	0
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	0	0	0
T24	2019	0	0	0
T29	0	354	0	0
T49	0	41	0	0
T50	0	486	0	0
T101	0	1651	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T100
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T102
1	0	1	Covered	T1,T2,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	189251730	588555	0	0
DepthKnown_A	189697645	189485357	0	0
RvalidKnown_A	189697645	189485357	0	0
WreadyKnown_A	189697645	189485357	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	189442787	641240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189251730	588555	0	0
T1	2722	326	0	0
T2	1981	814	0	0
T3	1180	0	0	0
T4	0	36	0	0
T5	0	147	0	0
T7	2859	1305	0	0
T16	0	6498	0	0
T19	3199	0	0	0
T20	4127	0	0	0
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	0	0	0
T24	2019	0	0	0
T29	0	344	0	0
T49	0	56	0	0
T50	0	498	0	0
T101	0	1672	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	189442787	641240	0	0
T1	2722	326	0	0
T2	1981	814	0	0
T3	1180	0	0	0
T4	0	815	0	0
T5	0	1152	0	0
T7	2859	1305	0	0
T16	0	6498	0	0
T19	3199	0	0	0
T20	4127	0	0	0
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	0	0	0
T24	2019	0	0	0
T29	0	344	0	0
T49	0	56	0	0
T50	0	498	0	0
T101	0	1672	0	0