Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	698964	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5721816

1

T1

88

T2

35

T3

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1687803	1			T1	33		T2	106		T3	36
values[0x0]	2187353	1			T1	48		T2	15		T3	24
values[0x1]	2545624	1			T1	46		T2	20		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	342529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6078251

1

T1

100

T2

77

T3

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25414	1			T2	1		T11	1		T28	2
valid_sources[0x01]	24768	1			T1	1		T2	2		T29	1
valid_sources[0x02]	25578	1			T2	3		T4	1653		T40	83
valid_sources[0x03]	25168	1			T26	3		T29	1		T4	1684
valid_sources[0x04]	23482	1			T26	1		T4	1698		T20	1
valid_sources[0x05]	24198	1			T4	1797		T40	70		T233	1
valid_sources[0x06]	25120	1			T1	1		T28	3		T4	1654
valid_sources[0x07]	25980	1			T10	2		T26	1		T28	3
valid_sources[0x08]	25460	1			T2	2		T29	7		T4	1719
valid_sources[0x09]	24469	1			T11	1		T28	2		T4	1705
valid_sources[0x0a]	26050	1			T2	1		T4	1735		T44	2
valid_sources[0x0b]	24874	1			T2	4		T4	1678		T40	73
valid_sources[0x0c]	24966	1			T1	1		T10	1		T4	1762
valid_sources[0x0d]	26323	1			T11	1		T4	1747		T6	2
valid_sources[0x0e]	24209	1			T10	2		T4	1710		T42	1
valid_sources[0x0f]	23670	1			T1	1		T2	1		T4	1699
valid_sources[0x10]	24373	1			T1	1		T10	4		T29	2
valid_sources[0x11]	25189	1			T1	2		T10	3		T26	1
valid_sources[0x12]	25734	1			T2	1		T4	1647		T42	1
valid_sources[0x13]	22503	1			T1	1		T2	3		T10	10
valid_sources[0x14]	26007	1			T1	1		T26	1		T4	1689
valid_sources[0x15]	25523	1			T2	2		T26	2		T28	3
valid_sources[0x16]	25242	1			T2	1		T11	1		T4	1805
valid_sources[0x17]	24781	1			T10	1		T4	1752		T40	77
valid_sources[0x18]	26155	1			T4	1787		T42	2		T40	74
valid_sources[0x19]	23942	1			T1	1		T2	1		T11	1
valid_sources[0x1a]	24767	1			T1	1		T4	1687		T42	1
valid_sources[0x1b]	25789	1			T29	8		T4	1782		T40	98
valid_sources[0x1c]	24499	1			T4	1788		T44	1		T81	4
valid_sources[0x1d]	25964	1			T26	2		T4	1770		T20	1
valid_sources[0x1e]	24531	1			T2	1		T29	1		T4	1735
valid_sources[0x1f]	25486	1			T1	2		T3	2		T11	1
valid_sources[0x20]	23562	1			T4	1712		T42	2		T48	1
valid_sources[0x21]	25099	1			T2	2		T26	1		T4	1754
valid_sources[0x22]	24344	1			T28	14		T29	2		T4	1804
valid_sources[0x23]	25705	1			T1	1		T2	1		T28	2
valid_sources[0x24]	28488	1			T26	1		T4	1796		T40	80
valid_sources[0x25]	23865	1			T4	1744		T40	90		T98	4
valid_sources[0x26]	25686	1			T1	1		T26	2		T29	1
valid_sources[0x27]	24517	1			T4	1721		T6	2		T40	90
valid_sources[0x28]	26991	1			T1	3		T4	1758		T40	63
valid_sources[0x29]	24346	1			T1	1		T2	3		T11	1
valid_sources[0x2a]	25757	1			T1	1		T2	1		T11	1
valid_sources[0x2b]	26881	1			T2	2		T3	6		T10	1
valid_sources[0x2c]	24678	1			T10	7		T26	2		T4	1756
valid_sources[0x2d]	24266	1			T1	1		T3	3		T10	6
valid_sources[0x2e]	24332	1			T2	2		T26	1		T28	2
valid_sources[0x2f]	26707	1			T29	2		T4	1714		T20	3
valid_sources[0x30]	24428	1			T2	1		T10	11		T4	1726
valid_sources[0x31]	26030	1			T1	1		T2	1		T10	6
valid_sources[0x32]	23818	1			T1	1		T28	9		T4	1694
valid_sources[0x33]	25125	1			T1	2		T2	2		T26	1
valid_sources[0x34]	24980	1			T1	1		T2	1		T4	1670
valid_sources[0x35]	27990	1			T2	3		T4	1783		T6	4
valid_sources[0x36]	26803	1			T1	2		T26	1		T4	1699
valid_sources[0x37]	25688	1			T2	5		T3	37		T26	1
valid_sources[0x38]	25338	1			T1	2		T4	1727		T20	2
valid_sources[0x39]	24272	1			T1	2		T4	1764		T81	2
valid_sources[0x3a]	23894	1			T2	3		T10	4		T4	1887
valid_sources[0x3b]	25894	1			T2	1		T25	1		T26	2
valid_sources[0x3c]	24724	1			T26	2		T4	1691		T44	1
valid_sources[0x3d]	23548	1			T1	2		T10	6		T4	1792
valid_sources[0x3e]	23170	1			T1	3		T26	4		T29	1
valid_sources[0x3f]	25113	1			T4	1691		T20	1		T40	85
valid_sources[0x40]	25272	1			T4	1741		T6	1		T16	4
valid_sources[0x41]	23317	1			T2	2		T26	1		T4	1702
valid_sources[0x42]	24425	1			T2	1		T4	1720		T6	13
valid_sources[0x43]	23954	1			T4	1684		T44	2		T40	96
valid_sources[0x44]	24403	1			T11	1		T4	1713		T44	3
valid_sources[0x45]	26165	1			T1	1		T4	1682		T6	6
valid_sources[0x46]	28770	1			T1	1		T4	1747		T44	1
valid_sources[0x47]	24167	1			T1	1		T2	1		T10	2
valid_sources[0x48]	24176	1			T1	1		T3	2		T26	2
valid_sources[0x49]	24846	1			T1	1		T11	1		T26	1
valid_sources[0x4a]	22719	1			T2	1		T11	1		T29	1
valid_sources[0x4b]	24022	1			T1	1		T2	5		T26	1
valid_sources[0x4c]	25570	1			T2	2		T26	1		T4	1692
valid_sources[0x4d]	26765	1			T2	1		T26	1		T4	1653
valid_sources[0x4e]	25132	1			T11	1		T4	1711		T44	2
valid_sources[0x4f]	24727	1			T4	1732		T20	1		T40	81
valid_sources[0x50]	23335	1			T1	1		T4	1643		T42	8
valid_sources[0x51]	23196	1			T2	1		T10	1		T26	1
valid_sources[0x52]	25745	1			T10	4		T26	2		T4	1757
valid_sources[0x53]	26618	1			T1	1		T3	4		T10	6
valid_sources[0x54]	24141	1			T2	3		T4	1694		T6	1
valid_sources[0x55]	24913	1			T1	1		T11	1		T4	1829
valid_sources[0x56]	25317	1			T1	1		T10	5		T29	6
valid_sources[0x57]	25606	1			T4	1653		T44	1		T6	6
valid_sources[0x58]	24056	1			T1	1		T26	1		T28	1
valid_sources[0x59]	26221	1			T26	2		T4	1761		T40	88
valid_sources[0x5a]	24572	1			T1	1		T2	1		T11	1
valid_sources[0x5b]	23510	1			T1	1		T2	1		T3	2
valid_sources[0x5c]	25752	1			T4	1696		T6	27		T40	66
valid_sources[0x5d]	23833	1			T3	2		T11	1		T4	1690
valid_sources[0x5e]	25975	1			T2	1		T4	1777		T40	57
valid_sources[0x5f]	24118	1			T2	2		T25	42		T28	4
valid_sources[0x60]	24196	1			T11	3		T4	1722		T48	1
valid_sources[0x61]	24115	1			T1	1		T2	1		T3	1
valid_sources[0x62]	25391	1			T1	1		T26	1		T4	1771
valid_sources[0x63]	26534	1			T4	1795		T40	100		T98	3
valid_sources[0x64]	23852	1			T11	1		T26	1		T4	1712
valid_sources[0x65]	25674	1			T4	1709		T44	1		T40	87
valid_sources[0x66]	25164	1			T11	1		T4	1675		T40	81
valid_sources[0x67]	23472	1			T1	1		T25	1		T26	1
valid_sources[0x68]	24459	1			T1	1		T4	1849		T6	32
valid_sources[0x69]	22789	1			T26	1		T4	1695		T40	83
valid_sources[0x6a]	23723	1			T11	1		T26	1		T28	1
valid_sources[0x6b]	26207	1			T2	4		T10	1		T26	1
valid_sources[0x6c]	26340	1			T2	1		T3	6		T10	12
valid_sources[0x6d]	25734	1			T10	6		T4	1774		T40	80
valid_sources[0x6e]	25763	1			T10	5		T26	3		T4	1734
valid_sources[0x6f]	25089	1			T1	1		T2	3		T10	4
valid_sources[0x70]	25552	1			T1	1		T4	1758		T20	1
valid_sources[0x71]	24414	1			T1	2		T11	1		T26	2
valid_sources[0x72]	24735	1			T1	1		T2	2		T10	3
valid_sources[0x73]	25278	1			T26	1		T27	70		T4	1714
valid_sources[0x74]	24295	1			T1	1		T4	1756		T42	7
valid_sources[0x75]	24235	1			T11	1		T4	1714		T81	1
valid_sources[0x76]	23477	1			T26	2		T4	1759		T40	94
valid_sources[0x77]	24663	1			T1	1		T26	1		T4	1695
valid_sources[0x78]	26419	1			T10	1		T11	1		T26	1
valid_sources[0x79]	27015	1			T4	1734		T44	2		T6	11
valid_sources[0x7a]	26487	1			T4	1624		T81	2		T40	88
valid_sources[0x7b]	24145	1			T2	1		T26	1		T4	1786
valid_sources[0x7c]	23902	1			T26	3		T4	1716		T42	4
valid_sources[0x7d]	26251	1			T1	2		T2	1		T4	1755
valid_sources[0x7e]	24559	1			T10	7		T26	1		T4	1720
valid_sources[0x7f]	23707	1			T29	1		T4	1738		T20	3
valid_sources[0x80]	24727	1			T1	1		T4	1707		T42	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1439873

1

T1

1

T2

3

T3

12

values[0x0]

all_enables

biggest_size

2142072

1

T1

45

T2

14

T3

18

values[0x1]

all_enables

biggest_size

2139871

1

T1

42

T2

18

T3

21