Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2740	1			T1	1		T2	2		T10	2
non_zero_bins[1]	1976	1			T1	2		T2	1		T10	2
zero	9285	1			T2	1		T3	3		T25	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	494	1			T26	1		T28	1		T74	1
uni	3697	1			T2	1		T10	1		T11	1
gen	4496	1			T2	1		T3	2		T25	3
res	881	1			T1	1		T2	1		T10	2
ins	4433	1			T1	2		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9215

1

T1

1

T2

3

T25

1

mubi_true

4786

1

T1

2

T2

1

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

15

1

T11

1

T110

1

T271

1

pass

13986

1

T1

3

T2

4

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	121	1			T28	1		T40	1		T41	3
upd	non_zero_bins[0]	pass	mubi_true	124	1			T26	1		T4	4		T56	1
upd	non_zero_bins[1]	pass	mubi_false	70	1			T4	2		T40	1		T41	1
upd	non_zero_bins[1]	pass	mubi_true	88	1			T74	1		T4	2		T41	2
upd	zero	pass	mubi_false	49	1			T4	3		T6	1		T98	1
upd	zero	pass	mubi_true	42	1			T6	1		T41	2		T71	2
uni	zero	pass	mubi_false	2724	1			T2	1		T10	1		T11	1
uni	zero	pass	mubi_true	973	1			T4	22		T6	3		T43	1
gen	non_zero_bins[0]	pass	mubi_false	513	1			T2	1		T26	1		T4	10
gen	non_zero_bins[0]	pass	mubi_true	563	1			T10	1		T74	1		T4	16
gen	non_zero_bins[1]	pass	mubi_false	339	1			T27	1		T4	6		T40	1
gen	non_zero_bins[1]	pass	mubi_true	408	1			T4	6		T75	1		T76	1
gen	zero	fail	mubi_false	13	1			T110	1		T271	1		T280	1
gen	zero	pass	mubi_false	1946	1			T25	1		T11	2		T29	1
gen	zero	pass	mubi_true	714	1			T3	2		T25	2		T10	3
res	non_zero_bins[0]	pass	mubi_false	209	1			T4	4		T20	2		T41	4
res	non_zero_bins[0]	pass	mubi_true	173	1			T4	5		T69	1		T70	7
res	non_zero_bins[1]	pass	mubi_false	176	1			T2	1		T27	1		T40	1
res	non_zero_bins[1]	pass	mubi_true	149	1			T1	1		T10	2		T4	5
res	zero	fail	mubi_false	2	1			T11	1		T152	1		-	-
res	zero	pass	mubi_false	98	1			T4	3		T57	1		T41	1
res	zero	pass	mubi_true	74	1			T4	2		T40	1		T69	1
ins	non_zero_bins[0]	pass	mubi_false	544	1			T1	1		T10	1		T4	19
ins	non_zero_bins[0]	pass	mubi_true	493	1			T2	1		T4	9		T6	1
ins	non_zero_bins[1]	pass	mubi_false	382	1			T4	5		T44	1		T76	1
ins	non_zero_bins[1]	pass	mubi_true	364	1			T1	1		T26	1		T28	1
ins	zero	pass	mubi_false	2029	1			T11	1		T27	1		T29	1
ins	zero	pass	mubi_true	621	1			T3	1		T25	2		T11	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded