Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T33,T82
1	1	Covered	T3,T25,T11

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T25
1	0	Covered	T1,T3,T87
1	1	Covered	T1,T10,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T25,T11
1	0	Covered	T5,T15,T16

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T3,T25,T11
1	Covered	T5,T15,T16

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T3,T25,T11
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T25,T11
1	Covered	T5,T15,T16

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T25

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T10,T11
AutoCaptGenCnt	143	Covered	T1,T10,T11
AutoCaptReseedCnt	141	Covered	T1,T10,T11
AutoDispatch	125	Covered	T1,T10,T11
AutoFirstAckWait	119	Covered	T1,T10,T11
AutoLoadIns	69	Covered	T1,T10,T11
AutoSendGenCmd	150	Covered	T1,T10,T11
AutoSendReseedCmd	162	Covered	T1,T10,T11
BootDone	98	Covered	T11,T33,T74
BootGenAckWait	90	Covered	T25,T11,T33
BootInsAckWait	80	Covered	T3,T25,T11
BootLoadGen	85	Covered	T25,T11,T33
BootLoadIns	65	Covered	T3,T25,T11
BootLoadUni	102	Covered	T11,T74,T56
BootPulse	94	Covered	T11,T33,T74
BootUniAckWait	107	Covered	T11,T74,T56
Error	188	Covered	T5,T15,T16
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T3,T25,T11
SWPortMode	74	Covered	T2,T3,T25

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T10,T11
AutoAckWait->Error	188	Covered	T9,T108
AutoAckWait->Idle	211	Covered	T1,T23,T109
AutoAckWait->RejectCsrngEntropy	188	Covered	T29,T57,T110
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T10,T11
AutoCaptGenCnt->Error	188	Covered	T7,T111,T112
AutoCaptGenCnt->Idle	211	Covered	T109,T113,T114
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T87,T115,T116
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T10,T11
AutoCaptReseedCnt->Error	188	Covered	T117,T118,T119
AutoCaptReseedCnt->Idle	211	Covered	T23,T120,T121
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T122,T123,T124
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T10,T11
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T10,T11
AutoDispatch->Error	188	Covered	T125
AutoDispatch->Idle	138	Covered	T10,T20,T21
AutoDispatch->RejectCsrngEntropy	188	Covered	T126,T127,T128
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T10,T11
AutoFirstAckWait->Error	188	Covered	T129,T130
AutoFirstAckWait->Idle	211	Covered	T131,T132,T133
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T104,T102,T134
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T10,T11
AutoLoadIns->Error	188	Covered	T8,T135,T136
AutoLoadIns->Idle	211	Covered	T42,T80,T7
AutoLoadIns->RejectCsrngEntropy	188	Covered	T137,T138,T139
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T10,T11
AutoSendGenCmd->Error	188	Covered	T140,T141
AutoSendGenCmd->Idle	211	Covered	T142,T143,T144
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T145,T146,T147
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T10,T57
AutoSendReseedCmd->Error	188	Covered	T148,T149
AutoSendReseedCmd->Idle	211	Covered	T1,T150,T151
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T11,T152,T153
BootDone->BootLoadUni	102	Covered	T11,T74,T56
BootDone->Error	188	Covered	T60,T154,T155
BootDone->Idle	211	Covered	T82,T156,T157
BootDone->RejectCsrngEntropy	188	Covered	T42,T81,T80
BootGenAckWait->BootPulse	94	Covered	T11,T33,T74
BootGenAckWait->Error	188	Covered	T158
BootGenAckWait->Idle	211	Covered	T159,T160,T154
BootGenAckWait->RejectCsrngEntropy	188	Covered	T25,T161,T162
BootInsAckWait->BootLoadGen	85	Covered	T25,T11,T33
BootInsAckWait->Error	188	Covered	T163,T164,T165
BootInsAckWait->Idle	211	Covered	T33,T77,T166
BootInsAckWait->RejectCsrngEntropy	188	Covered	T3,T48,T167
BootLoadGen->BootGenAckWait	90	Covered	T25,T11,T33
BootLoadGen->Error	188	Covered	T168
BootLoadGen->Idle	211	Covered	T169,T170,T171
BootLoadGen->RejectCsrngEntropy	188	Covered	T172,T173,T174
BootLoadIns->BootInsAckWait	80	Covered	T3,T25,T11
BootLoadIns->Error	188	Covered	T175,T176,T177
BootLoadIns->Idle	211	Covered	T178,T179
BootLoadIns->RejectCsrngEntropy	188	Covered	T180,T181,T182
BootLoadUni->BootUniAckWait	107	Covered	T11,T74,T56
BootLoadUni->Error	188	Covered	T77,T183
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T184,T185,T186
BootPulse->BootDone	98	Covered	T11,T33,T74
BootPulse->Error	188	Covered	T187
BootPulse->Idle	211	Covered	T188,T189,T190
BootPulse->RejectCsrngEntropy	188	Covered	T191,T192,T193
BootUniAckWait->Error	188	Covered	T160
BootUniAckWait->Idle	112	Covered	T11,T74,T56
BootUniAckWait->RejectCsrngEntropy	188	Covered	T84,T194,T195
Idle->AutoLoadIns	69	Covered	T1,T10,T11
Idle->BootLoadIns	65	Covered	T3,T25,T11
Idle->Error	188	Covered	T17,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T3,T11,T42
Idle->SWPortMode	74	Covered	T2,T3,T25
RejectCsrngEntropy->Error	188	Covered	T16,T79,T196
RejectCsrngEntropy->Idle	211	Covered	T3,T25,T11
SWPortMode->Error	188	Covered	T5,T15,T50
SWPortMode->Idle	211	Covered	T3,T25,T29
SWPortMode->RejectCsrngEntropy	188	Covered	T25,T29,T48

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T11
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T25
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T11
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T11
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T11
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T11,T33
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T25,T11,T33
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T25,T11,T33
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T33,T74
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T11,T74,T56
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T11,T33,T42
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T74,T56
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T74,T56,T43
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T11,T74,T56
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T20,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T10,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T10,T11
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T10,T11
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T25
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T11
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T94,T95,T96

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T15,T16
1	0	1	-	Not Covered
1	0	0	-	Covered	T3,T25,T11
0	-	-	1	Covered	T1,T3,T25
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	233790812	130833	0	0
FpvSecCmErrorStEscalate_A	233790812	131748	0	0
u_state_regs_A	233753427	233587025	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	130833	0	0
T5	1761	1072	0	0
T6	23666	0	0	0
T7	0	590	0	0
T8	0	531	0	0
T15	1495	623	0	0
T16	666	362	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	395	0	0
T51	0	555	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1149	0	0
T78	0	418	0	0
T79	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	131748	0	0
T5	1761	1073	0	0
T6	23666	0	0	0
T7	0	591	0	0
T8	0	532	0	0
T15	1495	624	0	0
T16	666	363	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	396	0	0
T51	0	556	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1150	0	0
T78	0	419	0	0
T79	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233753427	233587025	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0