Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T25

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T10
DataWait	75	Covered	T1,T2,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T188,T197,T198
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T10
DataWait->AckPls	80	Covered	T1,T2,T10
DataWait->Disabled	107	Covered	T33,T166,T109
DataWait->Error	99	Covered	T16,T51,T7
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T199,T200,T201
EndPointClear->Error	99	Covered	T8,T135,T175
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T10
Idle->Disabled	107	Covered	T1,T3,T25
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T10
Idle	-	1	0	-	Covered	T1,T2,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T10
DataWait	-	-	-	0	Covered	T1,T2,T10
AckPls	-	-	-	-	Covered	T1,T2,T10
Error	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	Covered	T7,T77,T8

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T15,T16
0	1	Covered	T1,T3,T25
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1636535684	925531	0	0
FpvSecCmErrorStEscalate_A	1636535684	931936	0	0
u_state_regs_A	1636498299	1635333485	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1636535684	925531	0	0
T5	12327	7504	0	0
T6	165662	0	0	0
T7	0	4080	0	0
T8	0	3667	0	0
T15	10465	4361	0	0
T16	4662	2534	0	0
T43	29078	0	0	0
T44	16247	0	0	0
T48	12747	0	0	0
T50	5124	2765	0	0
T51	0	3885	0	0
T56	12873	0	0	0
T57	11207	0	0	0
T77	0	7993	0	0
T78	0	2876	0	0
T79	0	1140	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1636535684	931936	0	0
T5	12327	7511	0	0
T6	165662	0	0	0
T7	0	4087	0	0
T8	0	3674	0	0
T15	10465	4368	0	0
T16	4662	2541	0	0
T43	29078	0	0	0
T44	16247	0	0	0
T48	12747	0	0	0
T50	5124	2772	0	0
T51	0	3892	0	0
T56	12873	0	0	0
T57	11207	0	0	0
T77	0	8000	0	0
T78	0	2883	0	0
T79	0	1147	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1636498299	1635333485	0	0
T1	16933	16520	0	0
T2	23051	22400	0	0
T3	17024	16632	0	0
T10	40992	40383	0	0
T11	16926	16485	0	0
T25	13734	13118	0	0
T26	31276	30919	0	0
T27	11515	10920	0	0
T28	26537	26166	0	0
T29	17290	16695	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T25

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T10
DataWait	75	Covered	T1,T2,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T10
DataWait->AckPls	80	Covered	T1,T2,T10
DataWait->Disabled	107	Covered	T202,T203,T204
DataWait->Error	99	Covered	T9,T94,T96
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T199,T200,T201
EndPointClear->Error	99	Covered	T17,T18,T205
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T10
Idle->Disabled	107	Covered	T1,T3,T25
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T10
Idle	-	1	0	-	Covered	T1,T2,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T10
DataWait	-	-	-	0	Covered	T1,T2,T10
AckPls	-	-	-	-	Covered	T1,T2,T10
Error	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	Covered	T7,T77,T8

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T15,T16
0	1	Covered	T1,T3,T25
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	233790812	130033	0	0
FpvSecCmErrorStEscalate_A	233790812	130948	0	0
u_state_regs_A	233753427	233587025	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	130033	0	0
T5	1761	1072	0	0
T6	23666	0	0	0
T7	0	540	0	0
T8	0	481	0	0
T15	1495	623	0	0
T16	666	362	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	395	0	0
T51	0	555	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1099	0	0
T78	0	368	0	0
T79	0	120	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	130948	0	0
T5	1761	1073	0	0
T6	23666	0	0	0
T7	0	541	0	0
T8	0	482	0	0
T15	1495	624	0	0
T16	666	363	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	396	0	0
T51	0	556	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1100	0	0
T78	0	369	0	0
T79	0	121	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233753427	233587025	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T25

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T10,T26
DataWait	75	Covered	T2,T10,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T10,T26
DataWait->AckPls	80	Covered	T2,T10,T26
DataWait->Disabled	107	Covered	T206,T207,T208
DataWait->Error	99	Covered	T7,T196,T209
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T199,T200,T201
EndPointClear->Error	99	Covered	T8,T135,T175
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T10,T26
Idle->Disabled	107	Covered	T1,T3,T25
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T10,T26
Idle	-	1	0	-	Covered	T2,T10,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T10,T26
DataWait	-	-	-	0	Covered	T2,T10,T26
AckPls	-	-	-	-	Covered	T2,T10,T26
Error	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T15,T16
0	1	Covered	T1,T3,T25
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	233790812	132583	0	0
FpvSecCmErrorStEscalate_A	233790812	133498	0	0
u_state_regs_A	233790812	233624410	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	132583	0	0
T5	1761	1072	0	0
T6	23666	0	0	0
T7	0	590	0	0
T8	0	531	0	0
T15	1495	623	0	0
T16	666	362	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	395	0	0
T51	0	555	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1149	0	0
T78	0	418	0	0
T79	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	133498	0	0
T5	1761	1073	0	0
T6	23666	0	0	0
T7	0	591	0	0
T8	0	532	0	0
T15	1495	624	0	0
T16	666	363	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	396	0	0
T51	0	556	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1150	0	0
T78	0	419	0	0
T79	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T25

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T11,T26
DataWait	75	Covered	T2,T11,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T11,T26
DataWait->AckPls	80	Covered	T2,T11,T26
DataWait->Disabled	107	Covered	T33,T171,T210
DataWait->Error	99	Covered	T16,T51,T165
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T199,T200,T201
EndPointClear->Error	99	Covered	T8,T135,T175
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T11,T26
Idle->Disabled	107	Covered	T1,T3,T25
Idle->Error	99	Covered	T5,T15,T50

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T11,T26
Idle	-	1	0	-	Covered	T2,T11,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T11,T26
DataWait	-	-	-	0	Covered	T2,T26,T29
AckPls	-	-	-	-	Covered	T2,T11,T26
Error	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T15,T16
0	1	Covered	T1,T3,T25
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	233790812	132583	0	0
FpvSecCmErrorStEscalate_A	233790812	133498	0	0
u_state_regs_A	233790812	233624410	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	132583	0	0
T5	1761	1072	0	0
T6	23666	0	0	0
T7	0	590	0	0
T8	0	531	0	0
T15	1495	623	0	0
T16	666	362	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	395	0	0
T51	0	555	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1149	0	0
T78	0	418	0	0
T79	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	133498	0	0
T5	1761	1073	0	0
T6	23666	0	0	0
T7	0	591	0	0
T8	0	532	0	0
T15	1495	624	0	0
T16	666	363	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	396	0	0
T51	0	556	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1150	0	0
T78	0	419	0	0
T79	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T25

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T10
DataWait	75	Covered	T2,T3,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T10
DataWait->AckPls	80	Covered	T2,T3,T10
DataWait->Disabled	107	Covered	T211,T144
DataWait->Error	99	Covered	T95,T154,T155
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T199,T200,T201
EndPointClear->Error	99	Covered	T8,T135,T175
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T10
Idle->Disabled	107	Covered	T1,T3,T25
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T10
Idle	-	1	0	-	Covered	T2,T3,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T10
DataWait	-	-	-	0	Covered	T2,T3,T10
AckPls	-	-	-	-	Covered	T2,T3,T10
Error	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T15,T16
0	1	Covered	T1,T3,T25
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	233790812	132583	0	0
FpvSecCmErrorStEscalate_A	233790812	133498	0	0
u_state_regs_A	233790812	233624410	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	132583	0	0
T5	1761	1072	0	0
T6	23666	0	0	0
T7	0	590	0	0
T8	0	531	0	0
T15	1495	623	0	0
T16	666	362	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	395	0	0
T51	0	555	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1149	0	0
T78	0	418	0	0
T79	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	133498	0	0
T5	1761	1073	0	0
T6	23666	0	0	0
T7	0	591	0	0
T8	0	532	0	0
T15	1495	624	0	0
T16	666	363	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	396	0	0
T51	0	556	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1150	0	0
T78	0	419	0	0
T79	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T25

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T10,T42
DataWait	75	Covered	T2,T10,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T197,T212
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T10,T42
DataWait->AckPls	80	Covered	T2,T10,T42
DataWait->Disabled	107	Covered	T166,T109,T170
DataWait->Error	99	Covered	T77,T160,T112
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T199,T200,T201
EndPointClear->Error	99	Covered	T8,T135,T175
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T10,T42
Idle->Disabled	107	Covered	T1,T3,T25
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T10,T42
Idle	-	1	0	-	Covered	T2,T10,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T10,T42
DataWait	-	-	-	0	Covered	T2,T10,T42
AckPls	-	-	-	-	Covered	T2,T10,T42
Error	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T15,T16
0	1	Covered	T1,T3,T25
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	233790812	132583	0	0
FpvSecCmErrorStEscalate_A	233790812	133498	0	0
u_state_regs_A	233790812	233624410	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	132583	0	0
T5	1761	1072	0	0
T6	23666	0	0	0
T7	0	590	0	0
T8	0	531	0	0
T15	1495	623	0	0
T16	666	362	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	395	0	0
T51	0	555	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1149	0	0
T78	0	418	0	0
T79	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	133498	0	0
T5	1761	1073	0	0
T6	23666	0	0	0
T7	0	591	0	0
T8	0	532	0	0
T15	1495	624	0	0
T16	666	363	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	396	0	0
T51	0	556	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1150	0	0
T78	0	419	0	0
T79	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T25

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T25,T10
DataWait	75	Covered	T2,T25,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T198
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T25,T10
DataWait->AckPls	80	Covered	T2,T25,T10
DataWait->Disabled	107	Covered	T169,T113,T213
DataWait->Error	99	Covered	T129,T136,T214
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T199,T200,T201
EndPointClear->Error	99	Covered	T8,T135,T175
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T25,T10
Idle->Disabled	107	Covered	T1,T3,T25
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T25,T10
Idle	-	1	0	-	Covered	T2,T25,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T25,T10
DataWait	-	-	-	0	Covered	T2,T25,T10
AckPls	-	-	-	-	Covered	T2,T25,T10
Error	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T15,T16
0	1	Covered	T1,T3,T25
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	233790812	132583	0	0
FpvSecCmErrorStEscalate_A	233790812	133498	0	0
u_state_regs_A	233790812	233624410	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	132583	0	0
T5	1761	1072	0	0
T6	23666	0	0	0
T7	0	590	0	0
T8	0	531	0	0
T15	1495	623	0	0
T16	666	362	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	395	0	0
T51	0	555	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1149	0	0
T78	0	418	0	0
T79	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	133498	0	0
T5	1761	1073	0	0
T6	23666	0	0	0
T7	0	591	0	0
T8	0	532	0	0
T15	1495	624	0	0
T16	666	363	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	396	0	0
T51	0	556	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1150	0	0
T78	0	419	0	0
T79	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T25

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T10,T43
DataWait	75	Covered	T2,T10,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T188
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T10,T43
DataWait->AckPls	80	Covered	T2,T10,T43
DataWait->Disabled	107	Covered	T142,T215,T216
DataWait->Error	99	Covered	T217,T218
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T199,T200,T201
EndPointClear->Error	99	Covered	T8,T135,T175
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T10,T43
Idle->Disabled	107	Covered	T1,T3,T25
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T10,T43
Idle	-	1	0	-	Covered	T2,T10,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T10,T43
DataWait	-	-	-	0	Covered	T2,T10,T43
AckPls	-	-	-	-	Covered	T2,T10,T43
Error	-	-	-	-	Covered	T5,T15,T16
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T15,T16
0	1	Covered	T1,T3,T25
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	233790812	132583	0	0
FpvSecCmErrorStEscalate_A	233790812	133498	0	0
u_state_regs_A	233790812	233624410	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	132583	0	0
T5	1761	1072	0	0
T6	23666	0	0	0
T7	0	590	0	0
T8	0	531	0	0
T15	1495	623	0	0
T16	666	362	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	395	0	0
T51	0	555	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1149	0	0
T78	0	418	0	0
T79	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	133498	0	0
T5	1761	1073	0	0
T6	23666	0	0	0
T7	0	591	0	0
T8	0	532	0	0
T15	1495	624	0	0
T16	666	363	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	396	0	0
T51	0	556	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1150	0	0
T78	0	419	0	0
T79	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0