Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T91,T92
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T38,T39
1	0	1	Covered	T1,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466967964	1034562	0	0
DepthKnown_A	467581624	467248820	0	0
RvalidKnown_A	467581624	467248820	0	0
WreadyKnown_A	467581624	467248820	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	467318802	1121476	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466967964	1034562	0	0
T1	4838	3236	0	0
T2	6586	0	0	0
T3	4864	246	0	0
T10	11712	8166	0	0
T11	4836	487	0	0
T20	0	10894	0	0
T25	3924	0	0	0
T26	8936	0	0	0
T27	3290	0	0	0
T28	7582	0	0	0
T29	4940	578	0	0
T42	0	277	0	0
T57	0	459	0	0
T80	0	143	0	0
T87	0	1010	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467581624	467248820	0	0
T1	4838	4720	0	0
T2	6586	6400	0	0
T3	4864	4752	0	0
T10	11712	11538	0	0
T11	4836	4710	0	0
T25	3924	3748	0	0
T26	8936	8834	0	0
T27	3290	3120	0	0
T28	7582	7476	0	0
T29	4940	4770	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467581624	467248820	0	0
T1	4838	4720	0	0
T2	6586	6400	0	0
T3	4864	4752	0	0
T10	11712	11538	0	0
T11	4836	4710	0	0
T25	3924	3748	0	0
T26	8936	8834	0	0
T27	3290	3120	0	0
T28	7582	7476	0	0
T29	4940	4770	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467581624	467248820	0	0
T1	4838	4720	0	0
T2	6586	6400	0	0
T3	4864	4752	0	0
T10	11712	11538	0	0
T11	4836	4710	0	0
T25	3924	3748	0	0
T26	8936	8834	0	0
T27	3290	3120	0	0
T28	7582	7476	0	0
T29	4940	4770	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	467318802	1121476	0	0
T1	4838	3236	0	0
T2	6586	0	0	0
T3	4864	246	0	0
T5	0	220	0	0
T10	11712	8166	0	0
T11	4836	487	0	0
T16	0	292	0	0
T25	3924	0	0	0
T26	8936	0	0	0
T27	3290	0	0	0
T28	7582	0	0	0
T29	4940	578	0	0
T42	0	277	0	0
T50	0	279	0	0
T57	0	459	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T92
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T39
1	0	1	Covered	T1,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	233483982	512003	0	0
DepthKnown_A	233790812	233624410	0	0
RvalidKnown_A	233790812	233624410	0	0
WreadyKnown_A	233790812	233624410	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	233659401	555255	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233483982	512003	0	0
T1	2419	1599	0	0
T2	3293	0	0	0
T3	2432	94	0	0
T10	5856	4083	0	0
T11	2418	163	0	0
T20	0	5404	0	0
T25	1962	0	0	0
T26	4468	0	0	0
T27	1645	0	0	0
T28	3791	0	0	0
T29	2470	292	0	0
T42	0	127	0	0
T57	0	230	0	0
T80	0	34	0	0
T87	0	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	233659401	555255	0	0
T1	2419	1599	0	0
T2	3293	0	0	0
T3	2432	94	0	0
T5	0	111	0	0
T10	5856	4083	0	0
T11	2418	163	0	0
T16	0	147	0	0
T25	1962	0	0	0
T26	4468	0	0	0
T27	1645	0	0	0
T28	3791	0	0	0
T29	2470	292	0	0
T42	0	127	0	0
T50	0	145	0	0
T57	0	230	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T91
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T93
1	0	1	Covered	T1,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	233483982	522559	0	0
DepthKnown_A	233790812	233624410	0	0
RvalidKnown_A	233790812	233624410	0	0
WreadyKnown_A	233790812	233624410	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	233659401	566221	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233483982	522559	0	0
T1	2419	1637	0	0
T2	3293	0	0	0
T3	2432	152	0	0
T10	5856	4083	0	0
T11	2418	324	0	0
T20	0	5490	0	0
T25	1962	0	0	0
T26	4468	0	0	0
T27	1645	0	0	0
T28	3791	0	0	0
T29	2470	286	0	0
T42	0	150	0	0
T57	0	229	0	0
T80	0	109	0	0
T87	0	554	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	233659401	566221	0	0
T1	2419	1637	0	0
T2	3293	0	0	0
T3	2432	152	0	0
T5	0	109	0	0
T10	5856	4083	0	0
T11	2418	324	0	0
T16	0	145	0	0
T25	1962	0	0	0
T26	4468	0	0	0
T27	1645	0	0	0
T28	3791	0	0	0
T29	2470	286	0	0
T42	0	150	0	0
T50	0	134	0	0
T57	0	229	0	0