Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	619862	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4984612

1

T1

53

T2

240

T3

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1481346	1			T1	27		T2	581		T3	35
values[0x0]	1903763	1			T1	32		T2	29		T3	21
values[0x1]	2219365	1			T1	25		T2	26		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	305897	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5298577

1

T1

67

T2

352

T3

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22428	1			T1	1		T9	1		T21	386
valid_sources[0x01]	22135	1			T3	3		T34	134		T35	174
valid_sources[0x02]	21227	1			T23	2		T34	164		T35	616
valid_sources[0x03]	21156	1			T3	1		T9	1		T23	12
valid_sources[0x04]	22082	1			T9	1		T23	2		T34	207
valid_sources[0x05]	23771	1			T13	1		T61	6		T23	4
valid_sources[0x06]	21258	1			T1	3		T9	1		T23	11
valid_sources[0x07]	21067	1			T8	1		T9	1		T23	7
valid_sources[0x08]	22846	1			T3	2		T23	9		T58	2
valid_sources[0x09]	23114	1			T23	4		T34	294		T35	517
valid_sources[0x0a]	21283	1			T5	32		T34	173		T35	68
valid_sources[0x0b]	21457	1			T1	3		T64	4		T34	286
valid_sources[0x0c]	21763	1			T1	2		T9	2		T23	1
valid_sources[0x0d]	21303	1			T1	1		T8	2		T23	2
valid_sources[0x0e]	21295	1			T8	1		T23	7		T63	1
valid_sources[0x0f]	22104	1			T1	2		T23	1		T34	318
valid_sources[0x10]	22466	1			T1	1		T3	3		T9	1
valid_sources[0x11]	22085	1			T1	2		T3	1		T58	1
valid_sources[0x12]	22222	1			T3	1		T9	1		T23	4
valid_sources[0x13]	23225	1			T13	1		T23	6		T63	2
valid_sources[0x14]	21639	1			T2	3		T13	1		T23	3
valid_sources[0x15]	23214	1			T1	1		T2	55		T20	1
valid_sources[0x16]	22033	1			T61	1		T23	1		T34	98
valid_sources[0x17]	20930	1			T2	11		T3	1		T23	7
valid_sources[0x18]	20629	1			T2	31		T9	1		T34	450
valid_sources[0x19]	21777	1			T8	1		T23	11		T34	144
valid_sources[0x1a]	21664	1			T3	1		T5	3		T23	5
valid_sources[0x1b]	20433	1			T61	1		T23	1		T34	234
valid_sources[0x1c]	21251	1			T9	4		T61	2		T23	4
valid_sources[0x1d]	22437	1			T20	10		T23	4		T58	1
valid_sources[0x1e]	22527	1			T8	1		T34	353		T35	10
valid_sources[0x1f]	21599	1			T8	1		T9	1		T61	1
valid_sources[0x20]	21691	1			T23	1		T63	1		T34	331
valid_sources[0x21]	21344	1			T2	20		T69	48		T34	308
valid_sources[0x22]	21801	1			T3	1		T13	1		T23	1
valid_sources[0x23]	22549	1			T23	4		T34	170		T35	538
valid_sources[0x24]	22398	1			T3	1		T9	1		T23	4
valid_sources[0x25]	21933	1			T1	1		T2	9		T8	1
valid_sources[0x26]	22459	1			T9	1		T61	2		T58	2
valid_sources[0x27]	20522	1			T8	1		T23	7		T34	188
valid_sources[0x28]	20200	1			T3	3		T8	1		T34	366
valid_sources[0x29]	20865	1			T23	4		T63	2		T34	253
valid_sources[0x2a]	23026	1			T34	448		T35	59		T36	81
valid_sources[0x2b]	24185	1			T23	4		T34	221		T35	460
valid_sources[0x2c]	22009	1			T9	1		T13	2		T61	2
valid_sources[0x2d]	20565	1			T9	1		T23	7		T34	212
valid_sources[0x2e]	22476	1			T1	1		T13	1		T61	2
valid_sources[0x2f]	22773	1			T3	4		T23	3		T34	254
valid_sources[0x30]	22561	1			T2	31		T3	1		T8	1
valid_sources[0x31]	21664	1			T1	3		T23	4		T63	2
valid_sources[0x32]	21823	1			T8	1		T13	1		T58	1
valid_sources[0x33]	22357	1			T8	1		T9	1		T23	4
valid_sources[0x34]	21439	1			T2	18		T13	1		T23	4
valid_sources[0x35]	20992	1			T61	3		T23	4		T34	328
valid_sources[0x36]	20998	1			T13	1		T61	2		T23	4
valid_sources[0x37]	23106	1			T1	1		T3	1		T9	2
valid_sources[0x38]	20852	1			T1	1		T61	1		T23	5
valid_sources[0x39]	21291	1			T20	1		T61	1		T23	10
valid_sources[0x3a]	21687	1			T2	9		T13	1		T34	280
valid_sources[0x3b]	21833	1			T1	1		T13	3		T23	3
valid_sources[0x3c]	22183	1			T63	1		T34	247		T35	307
valid_sources[0x3d]	21621	1			T1	1		T13	1		T23	2
valid_sources[0x3e]	22240	1			T61	1		T23	10		T63	1
valid_sources[0x3f]	22764	1			T1	1		T20	1		T13	1
valid_sources[0x40]	20868	1			T13	1		T61	2		T23	9
valid_sources[0x41]	20891	1			T1	2		T13	1		T23	2
valid_sources[0x42]	20605	1			T23	15		T34	134		T35	200
valid_sources[0x43]	22378	1			T8	2		T13	2		T23	3
valid_sources[0x44]	21185	1			T13	1		T23	6		T34	182
valid_sources[0x45]	20907	1			T2	19		T61	1		T23	5
valid_sources[0x46]	20931	1			T23	2		T34	194		T35	234
valid_sources[0x47]	23469	1			T8	6		T13	1		T34	205
valid_sources[0x48]	22452	1			T1	1		T61	2		T23	4
valid_sources[0x49]	22764	1			T2	9		T8	1		T20	2
valid_sources[0x4a]	25359	1			T3	1		T9	1		T13	1
valid_sources[0x4b]	21586	1			T2	17		T8	1		T34	356
valid_sources[0x4c]	20749	1			T1	1		T23	1		T34	350
valid_sources[0x4d]	22316	1			T13	1		T23	3		T34	227
valid_sources[0x4e]	21914	1			T23	5		T34	188		T35	301
valid_sources[0x4f]	20603	1			T23	10		T34	106		T35	58
valid_sources[0x50]	21339	1			T1	1		T23	1		T63	1
valid_sources[0x51]	22624	1			T1	1		T23	5		T58	1
valid_sources[0x52]	22312	1			T22	2		T34	386		T35	212
valid_sources[0x53]	21286	1			T3	2		T8	1		T9	9
valid_sources[0x54]	20592	1			T2	27		T20	4		T13	1
valid_sources[0x55]	22508	1			T9	1		T23	1		T58	1
valid_sources[0x56]	21332	1			T3	2		T37	110		T13	1
valid_sources[0x57]	22194	1			T1	1		T3	1		T8	1
valid_sources[0x58]	20885	1			T1	1		T3	4		T13	1
valid_sources[0x59]	22034	1			T1	1		T2	21		T23	6
valid_sources[0x5a]	21115	1			T9	1		T61	5		T23	1
valid_sources[0x5b]	21025	1			T1	2		T9	2		T5	11
valid_sources[0x5c]	21289	1			T1	1		T20	1		T23	2
valid_sources[0x5d]	22295	1			T20	1		T61	4		T23	3
valid_sources[0x5e]	21097	1			T3	2		T8	1		T63	1
valid_sources[0x5f]	22148	1			T9	2		T23	3		T58	1
valid_sources[0x60]	20650	1			T1	2		T34	280		T35	12
valid_sources[0x61]	22391	1			T1	1		T13	1		T23	2
valid_sources[0x62]	21516	1			T61	1		T34	279		T35	18
valid_sources[0x63]	22090	1			T19	5		T9	1		T23	3
valid_sources[0x64]	22356	1			T63	3		T34	348		T35	93
valid_sources[0x65]	22514	1			T1	1		T23	3		T63	2
valid_sources[0x66]	21695	1			T8	1		T20	2		T23	5
valid_sources[0x67]	20391	1			T23	2		T63	1		T34	89
valid_sources[0x68]	22251	1			T13	1		T23	2		T58	1
valid_sources[0x69]	22527	1			T2	7		T3	2		T8	1
valid_sources[0x6a]	22329	1			T23	8		T34	317		T35	110
valid_sources[0x6b]	24127	1			T2	34		T23	8		T58	1
valid_sources[0x6c]	22056	1			T23	2		T34	218		T35	189
valid_sources[0x6d]	21668	1			T34	262		T35	280		T36	80
valid_sources[0x6e]	21422	1			T23	6		T58	1		T63	1
valid_sources[0x6f]	20745	1			T1	2		T2	33		T3	3
valid_sources[0x70]	22135	1			T1	2		T61	1		T23	3
valid_sources[0x71]	21472	1			T1	2		T3	1		T9	1
valid_sources[0x72]	22240	1			T3	1		T9	1		T34	215
valid_sources[0x73]	22965	1			T9	1		T63	2		T34	85
valid_sources[0x74]	23208	1			T2	5		T13	1		T23	3
valid_sources[0x75]	21429	1			T2	10		T13	1		T61	5
valid_sources[0x76]	24136	1			T23	10		T34	193		T35	15
valid_sources[0x77]	21971	1			T34	86		T35	584		T6	1
valid_sources[0x78]	20583	1			T1	1		T8	1		T61	3
valid_sources[0x79]	20643	1			T13	4		T23	4		T63	2
valid_sources[0x7a]	20630	1			T23	4		T34	361		T35	30
valid_sources[0x7b]	21370	1			T3	1		T13	1		T61	1
valid_sources[0x7c]	21351	1			T13	1		T34	316		T35	97
valid_sources[0x7d]	21569	1			T3	1		T23	6		T34	320
valid_sources[0x7e]	21972	1			T9	4		T23	2		T34	227
valid_sources[0x7f]	22225	1			T1	1		T8	1		T13	1
valid_sources[0x80]	21178	1			T63	2		T34	222		T35	151

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1254899

1

T1

3

T2

218

T3

3

values[0x0]

all_enables

biggest_size

1864359

1

T1

28

T2

14

T3

19

values[0x1]

all_enables

biggest_size

1865354

1

T1

22

T2

8

T3

27